Signal assignments 
Author Message
 Signal assignments

Hi,
Is there anyone who knows how to implement the following idea in a manner that
works.

    signal out : std_logic_vector(15 downto 0);
    signal in  : std_logic_vector( 7 downto 0);
    ...
    out <= (7 downto 0 => in, others => '0'); -- does not work!

I know I could do the following:

    out(7 downto 0) <= in;
    out(15 downto 8) <= (others =>'0');

but if I need to change the width of the variable "in", I'll have a lot of
typing to do to fix everything.

What I'm looking for is a way to implement the following idea:

    out <= (in'range => in, others => '0');

Thanks

--
**************************************************************
Daniel Dos Santos               CAE Electronics ltd
Hardware designer               Phone: (514) 341-2000 ext:3629
Visual Systems Engineering      Fax:   (514) 734-5618

**************************************************************



Sat, 12 Jan 2002 03:00:00 GMT  
 Signal assignments
Daniel,

I'll take a stab at it... You could build your output vector using a variable,
then assign the variable to out:

    variable var : std_logic_vector(15 downto 0);
    ...
    var := (others => '0');
    var(in'range) := in;
    out <= var;

I'm not 100% certain that my synthesizer would be happy assigning to
"var(in'range)".

Stephen

--------------------------------------------
Stephen Fraleigh
Ericsson, Inc.
Research Triangle Park, NC


Phone:  (919)472-6877
Fax:    (919)472-7451
--------------------------------------------

Quote:

> Hi,
> Is there anyone who knows how to implement the following idea in a manner that
> works.

>     signal out : std_logic_vector(15 downto 0);
>     signal in  : std_logic_vector( 7 downto 0);
>     ...
>     out <= (7 downto 0 => in, others => '0'); -- does not work!

> I know I could do the following:

>     out(7 downto 0) <= in;
>     out(15 downto 8) <= (others =>'0');

> but if I need to change the width of the variable "in", I'll have a lot of
> typing to do to fix everything.

> What I'm looking for is a way to implement the following idea:

>     out <= (in'range => in, others => '0');

> Thanks

> --
> **************************************************************
> Daniel Dos Santos               CAE Electronics ltd
> Hardware designer               Phone: (514) 341-2000 ext:3629
> Visual Systems Engineering      Fax:   (514) 734-5618

> **************************************************************



Sat, 12 Jan 2002 03:00:00 GMT  
 Signal assignments
I thought about it, but I have to make 40 others assignments that are similar.
I'm just wondering if there is a way to do it, otherwise I'll have to hardcode
it and pray that the signals width don't change.

Thanks.

Quote:

> I'll take a stab at it... You could build your output vector using a variable,
> then assign the variable to out:

>     variable var : std_logic_vector(15 downto 0);
>     ...
>     var := (others => '0');
>     var(in'range) := in;
>     out <= var;

--
**************************************************************
Daniel Dos Santos               CAE Electronics ltd
Hardware designer               Phone: (514) 341-2000 ext:3629
Visual Systems Engineering      Fax:   (514) 734-5618

**************************************************************


Sat, 12 Jan 2002 03:00:00 GMT  
 Signal assignments

Quote:

> Hi,
> Is there anyone who knows how to implement the following idea in a manner that
> works.

>     signal out : std_logic_vector(15 downto 0);
>     signal in  : std_logic_vector( 7 downto 0);
>     ...
>     out <= (7 downto 0 => in, others => '0'); -- does not work!

> I know I could do the following:

>     out(7 downto 0) <= in;
>     out(15 downto 8) <= (others =>'0');

> but if I need to change the width of the variable "in", I'll have a lot of
> typing to do to fix everything.

> What I'm looking for is a way to implement the following idea:

>     out <= (in'range => in, others => '0');

> Thanks

What do you think about using "for loop"?
I checked it in Design Compiler of Synopsys(c).

Library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity var_top_1 is
    port(
        a  : in  std_logic_vector( 5 downto 0);
        b  : in  std_logic_vector( 7 downto 0);
        c  : out std_logic_vector(15 downto 0);
        d  : out std_logic_vector(15 downto 0));
end var_top_1;
architecture code of var_top_1 is
begin
    p00 : process(a)
    begin
        c(15 downto (16-a'length)) <= a;
        for i in (15-a'length) downto 0 loop
            c(i) <='0';
        end loop;
    end process;
    p01 : process(b)
    begin
        d(15 downto (16-b'length)) <= b;
        for i in (15-b'length) downto 0 loop
            d(i) <='0';
        end loop;
    end process;
end code;

-- ***************************************
-- Kyungjin Jang
-- DIT 2R, Daewoo Electronics CO., LTD.
-- ***************************************



Sun, 13 Jan 2002 03:00:00 GMT  
 Signal assignments

Quote:

> Hi,
> Is there anyone who knows how to implement the following idea in a manner that
> works.

>     signal out : std_logic_vector(15 downto 0);
>     signal in  : std_logic_vector( 7 downto 0);
>     ...
>     out <= (7 downto 0 => in, others => '0'); -- does not work!

> I know I could do the following:

>     out(7 downto 0) <= in;
>     out(15 downto 8) <= (others =>'0');

> but if I need to change the width of the variable "in", I'll have a lot of
> typing to do to fix everything.

> What I'm looking for is a way to implement the following idea:

>     out <= (in'range => in, others => '0');

This statement cannot work because the signals in an aggregate have to be
elementary signals not vectors. You can aasign a range or individual parts of the
aggregate but not assign a vector to a range of the aggregate.

--
------------------------------------------
Dirk-Rolf Aust, Design Engineer

mikron AG
Am Soeldnermoos 17
D-85399 Hallbergmoos
Germany

Tel: +49-(0)811-5539-106
FAX: +49-(0)811-5539-413
------------------------------------------

  dirk.aust.vcf
< 1K Download


Sun, 13 Jan 2002 03:00:00 GMT  
 Signal assignments
Try this:

...............
output(output'high downto (output'low+input'low+1)) <= (others => '0');
output((output'high+input'high) downto output'low)  <= input;
...............

And forget signal names like 'in' or 'out', they are reserved names !

Andy

Quote:

> Hi,
> Is there anyone who knows how to implement the following idea in a manner that
> works.

>     signal out : std_logic_vector(15 downto 0);
>     signal in  : std_logic_vector( 7 downto 0);
>     ...
>     out <= (7 downto 0 => in, others => '0'); -- does not work!

> I know I could do the following:

>     out(7 downto 0) <= in;
>     out(15 downto 8) <= (others =>'0');

> but if I need to change the width of the variable "in", I'll have a lot of
> typing to do to fix everything.

> What I'm looking for is a way to implement the following idea:

>     out <= (in'range => in, others => '0');

> Thanks

> --
> **************************************************************
> Daniel Dos Santos               CAE Electronics ltd
> Hardware designer               Phone: (514) 341-2000 ext:3629
> Visual Systems Engineering      Fax:   (514) 734-5618

> **************************************************************



Sun, 13 Jan 2002 03:00:00 GMT  
 Signal assignments

Quote:

> I thought about it, but I have to make 40 others assignments that are similar.
> I'm just wondering if there is a way to do it, otherwise I'll have to hardcode
> it and pray that the signals width don't change.

> Thanks.


> > I'll take a stab at it... You could build your output vector using a variable,
> > then assign the variable to out:

> >     variable var : std_logic_vector(15 downto 0);
> >     ...
> >     var := (others => '0');
> >     var(in'range) := in;
> >     out <= var;

The same works with signals (two fewer lines of code per output signal
;-)
     OUTPUT <= (others => '0');
     OUTPUT(INPUT'range) <= INPUT;

Martin

--
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  Cauerstrasse 6, 91058 Erlangen, Germany, Fax: (+49) 9131 852-8699
           Martin Padeffke   Phone.: (+49) 9131 852-8690                

            W3 : http://www.vhdl-online.de/~padeffke  
              W3 : http://www.vhdl-online.de/~vhdl  
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Sun, 13 Jan 2002 03:00:00 GMT  
 Signal assignments

Quote:

> Hi,
> Is there anyone who knows how to implement the following idea in a manner that
> works.

>     signal out : std_logic_vector(15 downto 0);
>     signal in  : std_logic_vector( 7 downto 0);
>     ...
>     out <= (7 downto 0 => in, others => '0'); -- does not work!
> I know I could do the following:

>     out(7 downto 0) <= in;
>     out(15 downto 8) <= (others =>'0');

You may use the concat operator "&":

        out <= (15 downto 8 => '0') & in;

Quote:

> but if I need to change the width of the variable "in", I'll have a lot of
> typing to do to fix everything.

> What I'm looking for is a way to implement the following idea:

>     out <= (in'range => in, others => '0');

Try this

        out <= (out'length - 1 downto out'length - in'length => '0') & in;

--
Edwin



Sun, 13 Jan 2002 03:00:00 GMT  
 Signal assignments

Quote:

> Is there anyone who knows how to implement the following idea in a manner that
> works.

>     signal out : std_logic_vector(15 downto 0);
>     signal in  : std_logic_vector( 7 downto 0);
>     ...
>     out <= (7 downto 0 => in, others => '0'); -- does not work!

> I know I could do the following:

>     out(7 downto 0) <= in;
>     out(15 downto 8) <= (others =>'0');

> but if I need to change the width of the variable "in", I'll have a lot of
> typing to do to fix everything.

I think you're stuck with slices 'cos aggregates can only buildvalues element by
element..

Use attributes?

(names changed to pin & pout for compilation check)
Assuming pin is always assigned to lowest bits of pout...

pout(pin'high downto 0) <= pin;
pout(pout'high downto pin'length) <= (others => '0');

This'll still work when you change widths of pin & pout..

B

Esperan : the world's leading HDL and FPGA training company
www.esperan.com



Sun, 13 Jan 2002 03:00:00 GMT  
 Signal assignments

Quote:

> Hi,
> Is there anyone who knows how to implement the following idea in a manner that
> works.

>     signal out : std_logic_vector(15 downto 0);
>     signal in  : std_logic_vector( 7 downto 0);
>     ...
>     out <= (7 downto 0 => in, others => '0'); -- does not work!

> I know I could do the following:

>     out(7 downto 0) <= in;
>     out(15 downto 8) <= (others =>'0');

> but if I need to change the width of the variable "in", I'll have a lot of
> typing to do to fix everything.

> What I'm looking for is a way to implement the following idea:

>     out <= (in'range => in, others => '0');

> Thanks

> --
> **************************************************************
> Daniel Dos Santos               CAE Electronics ltd
> Hardware designer               Phone: (514) 341-2000 ext:3629
> Visual Systems Engineering      Fax:   (514) 734-5618

> **************************************************************

Try this:
   ...
   out                       <= (others => '0');
   out(in'length-1 downto 0) <= in;
   ...

(assuming you want to assign 'in' in the right-most bits of 'out')

Hope this helps.

--

      _/_/_/_/     _/_/_/     Andreas Gieriet, VP R&D
     _/     _/   _/          DS Diagonal Systems
    _/     _/     _/_/      phone:+41-1-905-6060

  _/_/_/_/     _/_/_/     http://www.diagonal.com/



Sun, 13 Jan 2002 03:00:00 GMT  
 
 [ 10 post ] 

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