Asnchronous Counter 
Author Message
 Asnchronous Counter

Hi VHDL-Gurus!
Here is my question: I am trying to write the VHDL code for an
asynchronous counter (a ripple counter). In the simulation it works
OK, but when I check the synthesized version, I get lots of glitches.
Is there any way to eliminate them from the counting sequence? Any
idea?
Regards,
Luigi


Sat, 10 Sep 2005 20:06:13 GMT  
 Asnchronous Counter

Quote:
> Here is my question: I am trying to write the VHDL code for an
> asynchronous counter (a ripple counter). In the simulation it works
> OK, but when I check the synthesized version, I get lots of glitches.

Funny, that.  You probably get them in a real hardware ripple
counter, too.  I believe it's something to do with causality :-)

Quote:
> Is there any way to eliminate them from the counting sequence?

a) Teleport yourself into the never-never land of zero-delay
   simulation.
b) Don't use an asynchronous ripple counter.

Quote:
> Any idea?

Make sure you have a reasonably good idea of what digital
design is all about BEFORE you start coding in VHDL.
--
Jonathan Bromley, Consultant

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Sat, 10 Sep 2005 20:16:56 GMT  
 Asnchronous Counter

Quote:

> Hi VHDL-Gurus!
> Here is my question: I am trying to write the VHDL code for an
> asynchronous counter (a ripple counter). In the simulation it works
> OK, but when I check the synthesized version, I get lots of glitches.
> Is there any way to eliminate them from the counting sequence? Any
> idea?
> Regards,
> Luigi

Hi, just work on the falling edge for your base clock, and work with the
   rising_edge to use the result of your asynchronous counter.
You can find example of that on
http://www.amontec.com/fix/core/amt_hdl_util/amt_hdl_utilindex.htm
and check the component named amt_s_fe_cnt_async_up (this is a generic
asynchronous counter working on the falling_edge)

Laurent Gauch
www.amontec.com



Sun, 11 Sep 2005 01:26:36 GMT  
 Asnchronous Counter

 > I am trying to write the VHDL code for an

Quote:
> asynchronous counter (a ripple counter). In the simulation it works
> OK, but when I check the synthesized version, I get lots of glitches.
> Is there any way to eliminate them from the counting sequence?

Consider adding a register to the output on the same clock.
The register output will be one tick delayed, but glitch free.

      --Mike Treseler



Sun, 11 Sep 2005 02:19:41 GMT  
 Asnchronous Counter

Quote:

>Hi VHDL-Gurus!
>Here is my question: I am trying to write the VHDL code for an
>asynchronous counter (a ripple counter). In the simulation it works
>OK, but when I check the synthesized version, I get lots of glitches.
>Is there any way to eliminate them from the counting sequence? Any
>idea?

Gray code.

- Brian



Sun, 11 Sep 2005 22:16:51 GMT  
 
 [ 5 post ] 

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