what is multisource 
Author Message
 what is multisource

Hi all

We're trying to build a PID controller in VHDL, and we're finally down to
the last problems... one of these is quite perplexing, since nobody seems to
know the answer we need.

The problem is, when trying to syntesize the following code for a Spartan2:
--------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity error is
 port( clk  : in STD_LOGIC;
  reset : in STD_LOGIC;
  wanted : in STD_LOGIC_VECTOR(7 downto 0);
  measured: in STD_LOGIC_VECTOR(7 downto 0);
  cor : out STD_LOGIC_VECTOR(7 downto 0));
end error;

architecture error_arch of error is
signal correctn : STD_LOGIC_VECTOR(7 downto 0);
--signal present : integer;  --Current error diff.
--signal last : integer;
begin
 process(clk, reset)
 begin
  if (reset='1') then
    cor <= "00000000";
   end if;
   if(clk='1' and CLK'event) then
    correctn <= signed(wanted)-signed(measured);
   end if;
 end process;
 cor<=correctn;
end error_arch;

----------------------------

We get this error message:

Starting low level synthesis...
WARNING:Xst:528 - Multi-source in Unit <error> on signal <XST_GND> not
replaced by logic
WARNING:Xst:529 - Sources are: XST_GND:G, correctn_1:Q, correctn_7:Q,
correctn_6:Q, correctn_5:Q, correctn_4:Q, correctn_3:Q
, correctn_2:Q, correctn_0:Q
ERROR:Xst:415 - Synthesis failed

----------------------------
What is the problem with signal correctn, I've tried many things but nothing
helps..sigh!

Any advice is greatly, and happily accepted.

Thanks
Thomas



Fri, 28 May 2004 05:20:06 GMT  
 what is multisource

Quote:

> The problem is, when trying to syntesize the following code for a Spartan2:
>  process(clk, reset)
>  begin
>   if (reset='1') then
>     cor <= "00000000";

    --end if;
    --if(clk='1' and CLK'event) then
    ------------------------------------
      elsif (clk='1' and CLK'event) then
    ------------------------------------
    -- Mike Treseler
Quote:
>     correctn <= signed(wanted)-signed(measured);
>    end if;
>  end process;
>  cor<=correctn;
> end error_arch;



Fri, 28 May 2004 13:28:09 GMT  
 what is multisource
Thomas,

I think you have two problems in your design.

1) Your reset-signal does not have priority over the clock signal.
   That is fixed as indicated by Mike, i.e. the stucture of the
   process should be:

   process(clk, reset)
   begin
     if reset = '1' then
       "reset all signals"
     elsif clk='1' and clk'event then
       "do your stuff"
     end if;
   end process;

2) The 'cor' signal has two drivers, the process and the concurrent
   statement after the process. I think you will get the desired result
   if you reset 'correctn' instead of 'cor' in the process.

   architecture error_arch of error is
   signal correctn : STD_LOGIC_VECTOR(7 downto 0);
   --signal present : integer;  --Current error diff.
   --signal last : integer;
   begin
   process(clk, reset)
     begin
       if (reset='1') then
         -- cor <= "00000000";
         correctn <= "00000000";
       -- end if;
       -- if(clk='1' and CLK'event) then
       elsif(clk='1' and CLK'event) then
         correctn <= signed(wanted)-signed(measured);
       end if;
     end process;
     cor<=correctn; -- Now this is the only driver for 'cor'
   end error_arch;

Hope this helps!

/Torbj?rn



Quote:

> > The problem is, when trying to syntesize the following code for a
Spartan2:

> >  process(clk, reset)
> >  begin
> >   if (reset='1') then
> >     cor <= "00000000";

>     --end if;
>     --if(clk='1' and CLK'event) then
>     ------------------------------------
>       elsif (clk='1' and CLK'event) then
>     ------------------------------------
>     -- Mike Treseler

> >     correctn <= signed(wanted)-signed(measured);
> >    end if;
> >  end process;
> >  cor<=correctn;
> > end error_arch;



Fri, 28 May 2004 16:35:29 GMT  
 what is multisource
i would be resetting the correctn value... not the cor.

...
process (clk, reset)
begin
    if Reset = '1' then
    correctn <= (others => '0');
    elsif rising_edge (clk) then
    correctn <= signed(wanted) - signed(measured);
    end if;
end process

cor <= correctn;
....
HTH

--
Benjamin Todd
European Organisation for Nuclear Research
SL SPS/LHC -- Control -- Timing Division
CERN, Geneva, Switzerland,  CH-1211
Building 864 Room 1 - A24


Quote:
> Hi all

> We're trying to build a PID controller in VHDL, and we're finally down to
> the last problems... one of these is quite perplexing, since nobody seems
to
> know the answer we need.

> The problem is, when trying to syntesize the following code for a
Spartan2:
> --------------------------------
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;

> entity error is
>  port( clk  : in STD_LOGIC;
>   reset : in STD_LOGIC;
>   wanted : in STD_LOGIC_VECTOR(7 downto 0);
>   measured: in STD_LOGIC_VECTOR(7 downto 0);
>   cor : out STD_LOGIC_VECTOR(7 downto 0));
> end error;

> architecture error_arch of error is
> signal correctn : STD_LOGIC_VECTOR(7 downto 0);
> --signal present : integer;  --Current error diff.
> --signal last : integer;
> begin
>  process(clk, reset)
>  begin
>   if (reset='1') then
>     cor <= "00000000";
>    end if;
>    if(clk='1' and CLK'event) then
>     correctn <= signed(wanted)-signed(measured);
>    end if;
>  end process;
>  cor<=correctn;
> end error_arch;

> ----------------------------

> We get this error message:

> Starting low level synthesis...
> WARNING:Xst:528 - Multi-source in Unit <error> on signal <XST_GND> not
> replaced by logic
> WARNING:Xst:529 - Sources are: XST_GND:G, correctn_1:Q, correctn_7:Q,
> correctn_6:Q, correctn_5:Q, correctn_4:Q, correctn_3:Q
> , correctn_2:Q, correctn_0:Q
> ERROR:Xst:415 - Synthesis failed

> ----------------------------
> What is the problem with signal correctn, I've tried many things but
nothing
> helps..sigh!

> Any advice is greatly, and happily accepted.

> Thanks
> Thomas



Fri, 28 May 2004 18:44:37 GMT  
 what is multisource
Everything is looking alot brighter, thanks alot everybody

-Thomas



Sat, 29 May 2004 00:03:25 GMT  
 what is multisource
Maybe you can change you code like this:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity error is
        port(
                clk  : in STD_LOGIC;
                reset : in STD_LOGIC;
                wanted : in STD_LOGIC_VECTOR(7 downto 0);
                measured: in STD_LOGIC_VECTOR(7 downto 0);
                cor : out STD_LOGIC_VECTOR(7 downto 0));
end error;

architecture error_arch of error is

        signal correctn : STD_LOGIC_VECTOR(7 downto 0);
        --signal present : integer;  --Current error diff.
        --signal last : integer;

begin
        process(clk, reset)
        begin
                if (reset='1') then
                        correctn <= (others => '0');
                else
                        if(clk='1' and CLK'event) then
                                correctn <=
signed(wanted)-signed(measured);
                        end if;
                end if;
        end process;
        cor<=correctn;
end error_arch;



Fri, 04 Jun 2004 17:36:33 GMT  
 
 [ 6 post ] 

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