Config. Spec. with generate loop. 
Author Message
 Config. Spec. with generate loop.

Question?

Using VHDL 87 how does one use a component specification to bind a
component
instantiation to an entity if the component is being instantiated from
within
a generate loop. e.g.:

entity comp_ent is
port(
  comp_port_a : in  bit;
  comp_port_b : out bit);
end comp_ent;

architecture comp_arch of comp_ent is
begin
  comp_port_b <= comp_port_a;
end comp_arch;

entity ent is
port(
    a : in  bit_vector(0 to 3);
    b : out bit_vector(0 to 3)
);
end ent;

architecture arch of ent is
  component comp
  port(
    comp_port_a : in  bit;
    comp_port_b : out bit);
  end component;
  -- for U1 : comp use entity work.comp_ent(comp_arc); -- gives error
msg.
     for U1 : comp use entity work.comp_ent(comp_arc); -- compiles ok
but
                                                       -- no binding
occurs
begin
  Mygen: for i in 0 to 3 generate
    U1: comp
      port map   (comp_port_a => a(i),
                  comp_port_b => b(i)
      );
  end generate Mygen;
end arch;

I gather from the LRM that elaboration of a generate statement creates a
separate block statement for each iteration of the generate loop. So my
guess is that the component specification as written above will not be
visible to the statement buried inside the block thus created. So how do
I create the
required visibility?

Thanks in advance

Steve Barnfield.

--

+------------------------------+----------------------------------+

|  IBM High Level Synthesis    |  tel Fishkill :1-914-892-9666    |
|  East Fishkill Facility      |  T/L Fishkill :      532-9666    |
|  1580 Rt. 52, Hopewell Jct.  |  tel Yorktown :1-914-945-2521    |
|  NY 12533.   U.S.A.          |  T/L Yorktown :      862-2521    |
+-----------------------------------------------------------------+



Tue, 28 Mar 2000 03:00:00 GMT  
 Config. Spec. with generate loop.

Sorry a small typo.
the 2nd component specification which compiles ok but fails to create
the
correct binding should read:

 for ALL : comp use entity work.comp_ent(comp_arch); -- compiles ok
                                                     -- but no binding.

I have now managed to get this to work by nesting the component instance
inside an explicit block statement and placing the component
specification
inside the declarative region of the block statement.

 begin
   Mygen: for i in 0 to 3 generate
     MyBlk: BLOCK
      for U1 : comp use entity work.comp_ent(comp_arch);    
     begin
     U1: comp
       port map   (comp_port_a => a(i),
                   comp_port_b => b(i)
       );
     end BLOCK MyBlk;
   end generate Mygen;
 end arch;

Not terribly elegant
but I guess thats why VHDL 93 has provided a declarative region for
generate
statements.

Steve Barnfield.

Quote:

> Question?

> Using VHDL 87 how does one use a component specification to bind a
> component
> instantiation to an entity if the component is being instantiated from
> within
> a generate loop. e.g.:

> entity comp_ent is
> port(
>   comp_port_a : in  bit;
>   comp_port_b : out bit);
> end comp_ent;

> architecture comp_arch of comp_ent is
> begin
>   comp_port_b <= comp_port_a;
> end comp_arch;

> entity ent is
> port(
>     a : in  bit_vector(0 to 3);
>     b : out bit_vector(0 to 3)
> );
> end ent;

> architecture arch of ent is
>   component comp
>   port(
>     comp_port_a : in  bit;
>     comp_port_b : out bit);
>   end component;
>   -- for U1 : comp use entity work.comp_ent(comp_arc); -- gives error
> msg.
>      for U1 : comp use entity work.comp_ent(comp_arc); -- compiles ok
> but
>                                                        -- no binding
> occurs
> begin
>   Mygen: for i in 0 to 3 generate
>     U1: comp
>       port map   (comp_port_a => a(i),
>                   comp_port_b => b(i)
>       );
>   end generate Mygen;
> end arch;

> I gather from the LRM that elaboration of a generate statement creates a
> separate block statement for each iteration of the generate loop. So my
> guess is that the component specification as written above will not be
> visible to the statement buried inside the block thus created. So how do
> I create the
> required visibility?

> Thanks in advance

> Steve Barnfield.

> --

> +------------------------------+----------------------------------+

> |  IBM High Level Synthesis    |  tel Fishkill :1-914-892-9666    |
> |  East Fishkill Facility      |  T/L Fishkill :      532-9666    |
> |  1580 Rt. 52, Hopewell Jct.  |  tel Yorktown :1-914-945-2521    |
> |  NY 12533.   U.S.A.          |  T/L Yorktown :      862-2521    |
> +-----------------------------------------------------------------+



Fri, 31 Mar 2000 03:00:00 GMT  
 Config. Spec. with generate loop.

Quote:

> I have now managed to get this to work by nesting the component instance
> inside an explicit block statement and placing the component
> specification
> inside the declarative region of the block statement.

This is the *only* way of doing it in VHDL'87. So you didn't just
manage to make this work, you found the best solution! Mind you, it is
the configuration specification which must be in the block, the
component declaration could still stay in the architecture.

--
  \0/    \0/ \     \ /     /  \0/   \0/
   |     /   /)     |     (\   \     |
__/ \___/\___/0\___/0\___/0\___/\___/ \__
Andy Rushton - TransEDA Limited UK



Fri, 07 Apr 2000 03:00:00 GMT  
 
 [ 3 post ] 

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