synthesizing VHDL 
Author Message
 synthesizing VHDL

It would be interesting to find out how other users of VHDL approach the following
synthesis problem. I am using VHDL 1076-87 only.

Most synthesizers treat a chain of if-then-elsif-elsif-elsif-elsif .... end if
as implying priority. In my experience, I do not need such priority encoding.
Consider the following:

if     a = '1'  then ...
elsif  b = '1'  then ...
elsif  c = '1'  then ...
elsif  d = '1'  then ...
else                 ...
end if;

This could be equivalently encoded as a case statement as:

vec := a & b & c & d;
case vec is
  when "1---" => ....
  when "01--" => ....
  when "001-" => ....
  when OTHERS => ....
end case;

No priority is implied and such code would synthesize to a smaller number of
gates and probably be faster too.
The problem comes when this second piece of RTL code is used for simulation.
A VHDL simulator does not recognize '-' to be don't care but tries to match
signal 'b' to '-' for example. 'b' will be nominally '1' or '0' and hence
will always fail the match to '-'.

One possibility is to automatically process the VHDL code before
analyzing  so that all -'s are replaced with a list of 0/1 alternatives
to generate code of the following form

  when "1000" | "1001" | "1010" | "1011" | "1100" | "1101" | "1110" | "1111" => ....
  when "0100" | "0101" | "0110" | "0111"                                     => ....
  ....

This can easily be done in C/PERL.... but does mean that the code that is simulated
at the RTL stage is different from the code that is synthesized.

What do you VHDL'ers think.

Andrew



Tue, 14 Jan 1997 00:49:55 GMT  
 synthesizing VHDL

Quote:

>It would be interesting to find out how other users of VHDL approach the
following
>synthesis problem. I am using VHDL 1076-87 only.

>Most synthesizers treat a chain of if-then-elsif-elsif-elsif-elsif .... end if
>as implying priority. In my experience, I do not need such priority encoding.
>Consider the following:

>if     a = '1'  then ...
>elsif  b = '1'  then ...
>elsif  c = '1'  then ...
>elsif  d = '1'  then ...
>else                 ...
>end if;

True, but synthesis will then tend to take out the priorities later on if it is
appropriate to the optimisation of the circuit. This is of course not
guaranteed and the initial circuit _will_ have this prioritisation as you say.

Quote:

>This could be equivalently encoded as a case statement as:

>vec := a & b & c & d;
>case vec is
>  when "1---" => ....
>  when "01--" => ....
>  when "001-" => ....
>  when OTHERS => ....
>end case;

>No priority is implied and such code would synthesize to a smaller number of
>gates and probably be faster too.

I have a feeling that this is larger, since you are making more tests (for
example, in branch 3 you are testing for a = '0', b = '0' _and_ c = '1'). It
will _possibly_ be quicker... but then again it might not be. Chances are
synthesis will reduce it to the same circuit anyway so why make the effort. 8-)

Quote:

>The problem comes when this second piece of RTL code is used for simulation.
>A VHDL simulator does not recognize '-' to be don't care but tries to match
>signal 'b' to '-' for example. 'b' will be nominally '1' or '0' and hence
>will always fail the match to '-'.

The following interpretation is recommended by the vhdlsynth working group for
the '-' value:

"The value '-' is called the don't care value, because when used as a source in
an assignment statement, it means the target object may be set to either state
without having an effect  on the system in which this description is used.  In
other words, it is an output don't  care, as opposed to an input don't care or
wild card."

In your example, you are using '-' as a wild card, which is not its intended
purpose and as you point out, will not be interpreted as such by simulation.
Synthesis works on the principle of what-you-simulate-is-what-you-get (WYSIWYG)
so you will not get the required behaviour from synthesis either.

Quote:
>One possibility is to automatically process the VHDL code before
>analyzing  so that all -'s are replaced with a list of 0/1 alternatives
>to generate code of the following form

>  when "1000" | "1001" | "1010" | "1011" | "1100" | "1101" | "1110" | "1111"
=> ....
>  when "0100" | "0101" | "0110" | "0111"                                    
=> ....
>  ....

This is the only way to do it - but you will have to do it by hand. The
resulting circuit is now much bigger due to all the extra tests and _might_ be
non-prioritised. If you are lucky it will reduce to the original circuit.

My advice is to stick to the if statements and trust the synthesiser to hammer
the circuit flat.

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Mon, 20 Jan 1997 17:19:01 GMT  
 
 [ 2 post ] 

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