Edif and VHDL 
Author Message
 Edif and VHDL

Imagine I have EDIF version of some component. ( just I have edif version ).

how can I use it in VHDL?

In better word how can I Undrestand its interface as a component in vhdl ?

any suggestion ?



Sun, 06 Jun 2004 14:46:47 GMT  
 Edif and VHDL

Quote:

> Imagine I have EDIF version of some component. ( just I have edif version ).

> how can I use it in VHDL?

> In better word how can I Undrestand its interface as a component in vhdl ?

> any suggestion ?

Instantiate in the normal way the component for which you have a netlist (I
assume you know its interface signals), and put a black box attribute on it
(your synthesis tool manual will tell you how).
When you come to load the design into your place & route tool, it will see the
blackbox attribute and expect to find a netlist for the component, and will
incorporate it into the design.  I am assuming here that you are using an FPGA?

This worked for me with Synplify and Xilinx Alliance.  Synplify automatically
blackboxes a component if it cannot find a corresponding entity in the library.
The components I did this for were Coregen modules.
HTH
--

Ericsson Microelectronics



Mon, 07 Jun 2004 20:04:59 GMT  
 
 [ 2 post ] 

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