when we using 'back-slash' 
Author Message
 when we using 'back-slash'

Hi,
  I am new to VHDL and therefore I might need your help on telling me this:

    signal \any_name\ : std_logic;

  What does the 'back-slash' means and when we using this ?

  Thanks in advance.



Fri, 16 Sep 2005 08:39:59 GMT  
 when we using 'back-slash'

Quote:

> Hi,
>   I am new to VHDL and therefore I might need your help on telling me this:

>     signal \any_name\ : std_logic;

>   What does the 'back-slash' means and when we using this ?

This is one of the things added into the language in the 1993
version of the LRM.

The "\" around the name is used to perserve case and some illegal
characters.  Mostly used for talking to Verilog, which is case
sensative.

--

http://www.vhdl.org/vhdlsynth/



Fri, 16 Sep 2005 11:23:34 GMT  
 
 [ 2 post ] 

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