Help on coding numerical algorithms using VHDL 
Author Message
 Help on coding numerical algorithms using VHDL

When implementing numerical algorithms (e.g. DCT) on FPGA using VHDL, do I
need
to translate my algorithm into logic function before I can code it in VHDL?
Or, is it
possible to describe a numerical algorithm directly using VHDL and let the
FPGA
tool to synthese the required logic function?

I have no experience on this. Thank for any help.

C. F. Fung



Sun, 02 Apr 2000 03:00:00 GMT  
 Help on coding numerical algorithms using VHDL

You can code your algorithms directly in VHDL and then synthesize to a
given FPGA family.  However, you may lose some efficiency.  The
resulting FPGA design will probably be larger and slower than if
custom-crafted for the application.

There are also some module generator packages that create the custom
logic for a given FPGA family.  In the case of the Xilinx tool, it also
generates a VHDL instantiation code fragment so that you can add the
function to a larger design.

Some links of interest include:

Xilinx press release that includes info on their DCT implementation.
It's buried in the release.
http://www.xilinx.com/prs_rls/reed_fft.htm .  They also have other DSP
functions (see
http://www.xilinx.com/products/logicore/tblcores.htm#DSPFunctions ).

Atmel's DSP Designer - http://www.atmel.com/atmel/news/19970707.html

-----------------------------------------------------------------------
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OptiMagic, Inc.

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|When implementing numerical algorithms (e.g. DCT) on FPGA using VHDL,
do I
|need
|to translate my algorithm into logic function before I can code it in
VHDL?
|Or, is it
|possible to describe a numerical algorithm directly using VHDL and let
the
|FPGA
|tool to synthese the required logic function?
|
|I have no experience on this. Thank for any help.
|
|C. F. Fung



Sun, 02 Apr 2000 03:00:00 GMT  
 Help on coding numerical algorithms using VHDL



Quote:
> When implementing numerical algorithms (e.g. DCT) on FPGA using VHDL, do
I
> need
> to translate my algorithm into logic function before I can code it in
VHDL?
> Or, is it
> possible to describe a numerical algorithm directly using VHDL and let
the
> FPGA
> tool to synthese the required logic function?

The answer to your question is no, you do NOT have to provide the
structural representation in VHDL prior to synthesis.  That is a function
of your software.

---BUT---

From your point of view, you will have to select a FPGA that is large
enough to fit what you are trying to accomplish.  Doing so blindly, with no
respect to synthesis, could be costly in the long haul, because you could
end up selecting a part that is larger than it needs to be (more gates ==
more $$$).  Many software systems allow the floor planner to optimize for
speed, for size, to balance, etc.  All that you can do is realize and test
the design first in the biggest part that you can afford, and THEN start
optimizing size, speed, both, etc. until you get it down to the size and
speed that you can afford.

Good luck.

pgd

--
"In matters of style, swim with the current; in matters of principle, stand
like a rock."
 -- Thomas Jefferson

Paul Duncan
Airak Engineering
RR3 Box 533
415 Chestnut Avenue
New Castle, VA  24127-9519
grems at swva dot net



Sat, 08 Apr 2000 03:00:00 GMT  
 
 [ 3 post ] 

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