Help on coding numerical algorithms using VHDL

Quote:

> When implementing numerical algorithms (e.g. DCT) on FPGA using VHDL, do

I

> need

> to translate my algorithm into logic function before I can code it in

VHDL?

> Or, is it

> possible to describe a numerical algorithm directly using VHDL and let

the

> FPGA

> tool to synthese the required logic function?

The answer to your question is no, you do NOT have to provide the

structural representation in VHDL prior to synthesis. That is a function

of your software.

---BUT---

From your point of view, you will have to select a FPGA that is large

enough to fit what you are trying to accomplish. Doing so blindly, with no

respect to synthesis, could be costly in the long haul, because you could

end up selecting a part that is larger than it needs to be (more gates ==

more $$$). Many software systems allow the floor planner to optimize for

speed, for size, to balance, etc. All that you can do is realize and test

the design first in the biggest part that you can afford, and THEN start

optimizing size, speed, both, etc. until you get it down to the size and

speed that you can afford.

Good luck.

pgd

--

"In matters of style, swim with the current; in matters of principle, stand

like a rock."

-- Thomas Jefferson

Paul Duncan

Airak Engineering

RR3 Box 533

415 Chestnut Avenue

New Castle, VA 24127-9519

grems at swva dot net