Simulation with synthesized output vhdl code 
Author Message
 Simulation with synthesized output vhdl code

        First, thank for your help...

        I have trouble in simulating with vhdl code that was generated

 from design_analyzer. Configuration is needed for module port

 mapped. But synthesized results does not contain configuration of

 each module. I want synthesized vhdl code contain configuration

 automatically like below...

        for all : gate_name use entity lib_name.gate_name(FTGS);

        Help me please.. Time before project due remains only 1 day..




Wed, 02 Dec 1998 03:00:00 GMT  
 Simulation with synthesized output vhdl code

Quote:

>         First, thank for your help...

>         I have trouble in simulating with vhdl code that was generated

>  from design_analyzer. Configuration is needed for module port

>  mapped. But synthesized results does not contain configuration of

>  each module. I want synthesized vhdl code contain configuration

>  automatically like below...

>         for all : gate_name use entity lib_name.gate_name(FTGS);

>         Help me please.. Time before project due remains only 1 day..



I have just the same problems with synopsys....


Fri, 04 Dec 1998 03:00:00 GMT  
 Simulation with synthesized output vhdl code

I can not give a satifying answer anymore, but when I worked
with this stuff I expirenced also problems.
They mostly came because in my original design I used bit and
bit_vector ports. Synopsys translates them to std_logic ports and
applies some interface function so you can use your old testbench.

The problem is, that in the original design the ports automaticly
were set to  '0'. Std_logic gates are set to 'U'. - And the logic
doesn"t know what to make of this.

A good solution to this problem would be to design already using
std_logic signals (ports) and to use a reset signal to set your
signals to a defined value. (I guess there would be a way to do
this without an extra reset signal, like an initial state.)

But also with using std_logic ports I had some difficulties,
simulating the design. For instance the software still implemented
a conversion function, that didn't work and had to be erased..

I did some presentation on this stuf an put it on the network.
The link is: http://www.ee.vt.edu/hadlich/doc/notes.ps.
The size is _80K_! The format is postscript (from Powerpoint).  

There was also an application note from synopsys about that stuff..

Good luck,

Thomas

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Sat, 05 Dec 1998 03:00:00 GMT  
 
 [ 3 post ] 

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