
Converting EDIF files or Viewdraw Schematics to VHDL
All it will get you is a structural netlist of the primitives in the edif
netlist. Don't expect it to be readable. You'll also need the simulation
models of the primitives. I don't know of PD software that does this, but there
are other options. 1) if you have or can get Aldec ActiveHDL, it can simulate
edif netlists, which is a nice feature. 2) you can generate a vhdl output file
from some of the vendor place and route tools. I know xilinx will do that, and
I'm pretty sure Altera will too.
Quote:
> Hi All,
> I'm looking for a shareware or public domain utility to convert EDIF files
> or Viewlogic schematic files to VHDL for simulation.
> Or alternatively, some method of doing this using Modelsim, Synopsys FPGA
> Express, the Xilinx FPGA tools, Exemplar Leonardo or Viewlogic Workview.
> Any suggestions?
> Thanks,
> Chris
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