Converting EDIF files or Viewdraw Schematics to VHDL 
Author Message
 Converting EDIF files or Viewdraw Schematics to VHDL

Hi All,

I'm looking for a shareware or public domain utility to convert EDIF files
or Viewlogic schematic files to VHDL for simulation.

Or alternatively, some method of doing this using Modelsim, Synopsys FPGA
Express, the Xilinx FPGA tools, Exemplar Leonardo or Viewlogic Workview.

Any suggestions?

Thanks,
Chris



Fri, 31 Jan 2003 03:00:00 GMT  
 Converting EDIF files or Viewdraw Schematics to VHDL
All it will get you is a structural netlist of the primitives in the edif
netlist.  Don't expect it to be readable.  You'll also need the simulation
models of the primitives.  I don't know of PD software that does this, but there
are other options.  1) if you have or can get Aldec ActiveHDL, it can simulate
edif netlists, which is a nice feature.  2) you can generate a vhdl output file
from some of the vendor place and route tools.  I know xilinx will do that, and
I'm pretty sure Altera will too.  

Quote:

> Hi All,

> I'm looking for a shareware or public domain utility to convert EDIF files
> or Viewlogic schematic files to VHDL for simulation.

> Or alternatively, some method of doing this using Modelsim, Synopsys FPGA
> Express, the Xilinx FPGA tools, Exemplar Leonardo or Viewlogic Workview.

> Any suggestions?

> Thanks,
> Chris

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950

http://www.andraka.com  or http://www.fpga-guru.com


Fri, 31 Jan 2003 03:00:00 GMT  
 Converting EDIF files or Viewdraw Schematics to VHDL
The primitives are not a problem - I already have VHDL models for all my
components. What I want is an automated process for producing a top-level
structural VHDL file of my top-level schematic, to ensure that I simulate
the same connectivity that I have on my PCB.

Chris


Quote:
> All it will get you is a structural netlist of the primitives in the edif
> netlist.  Don't expect it to be readable.  You'll also need the simulation
> models of the primitives.  I don't know of PD software that does this, but
there
> are other options.  1) if you have or can get Aldec ActiveHDL, it can
simulate
> edif netlists, which is a nice feature.  2) you can generate a vhdl output
file
> from some of the vendor place and route tools.  I know xilinx will do
that, and
> I'm pretty sure Altera will too.


> > Hi All,

> > I'm looking for a shareware or public domain utility to convert EDIF
files
> > or Viewlogic schematic files to VHDL for simulation.

> > Or alternatively, some method of doing this using Modelsim, Synopsys
FPGA
> > Express, the Xilinx FPGA tools, Exemplar Leonardo or Viewlogic Workview.

> > Any suggestions?

> > Thanks,
> > Chris

> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950

> http://www.andraka.com  or http://www.fpga-guru.com



Sat, 01 Feb 2003 14:09:32 GMT  
 Converting EDIF files or Viewdraw Schematics to VHDL

Quote:

>Hi All,

>I'm looking for a shareware or public domain utility to convert EDIF files
>or Viewlogic schematic files to VHDL for simulation.

>Or alternatively, some method of doing this using Modelsim, Synopsys FPGA
>Express, the Xilinx FPGA tools, Exemplar Leonardo or Viewlogic Workview.

>Any suggestions?

>Thanks,
>Chris

I thought Viewdraw could already do this? My understanding of the
brochure is that it can directly export vhdl from the schematic.

If you can't do this, and since you've got the Xilinx software, one
route is ngdbuild to generate an ngd from the edif, and ngd2vhdl to
generate a vhdl netlist from the ngd. However, this won't work with
2.1 since you can't get a kosher ngd file from your board-level
components. It may now be possible with 3.1, since I think that you
can now generate an incomplete ngd to support the 'modular design'
flow. I haven't got 3.1 yet so I can't run ngdbuild to check...

Evan



Sat, 01 Feb 2003 03:00:00 GMT  
 Converting EDIF files or Viewdraw Schematics to VHDL

Quote:

>Hi All,

>I'm looking for a shareware or public domain utility to convert EDIF files
>or Viewlogic schematic files to VHDL for simulation.

>Or alternatively, some method of doing this using Modelsim, Synopsys FPGA
>Express, the Xilinx FPGA tools, Exemplar Leonardo or Viewlogic Workview.

I understand that Leonardo can read in an EDIF file and write out the
same thing in VHDL. Haven't tried it, can't vouch for the usability of
the resulting VHDL, but I'd expect the connectivity at least to be
intact.

- Brian



Sat, 01 Feb 2003 03:00:00 GMT  
 Converting EDIF files or Viewdraw Schematics to VHDL

Quote:

> Hi All,

> I'm looking for a shareware or public domain utility to convert EDIF files
> or Viewlogic schematic files to VHDL for simulation.

> Or alternatively, some method of doing this using Modelsim, Synopsys FPGA
> Express, the Xilinx FPGA tools, Exemplar Leonardo or Viewlogic Workview.

You can read the EDIF with Design Analyzer of Synopsys and this one export in
vhdl or verilog and the sdf of the file.
in your .synopsys_dc.setup, you need to indicate the librairy of your
components.

Regis Caillet



Sat, 15 Feb 2003 03:00:00 GMT  
 
 [ 6 post ] 

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