VIUF Fall 1998 Prelim Call for Papers 
Author Message
 VIUF Fall 1998 Prelim Call for Papers

VHDL International Users' Forum

                            October, 1998

                         Preliminary Call for
                   Workshops, Tutorials and Papers

                 "Idea Factory: VHDL for Power Users"

                        http://www.*-*-*.com/

Over the past ten years, the EDA Industry has seen VHDL and some of
its satellite standards evolve from infancy to maturity.  The time for
"introducting" VHDL to the user community is long past; VIUF must
address the needs of a more experienced user base.  In light of this,
the Steering Committee for VIUF Fall 1998 has chosen to diverge from
the usual conference format.

Traditionally, Fall VIUFs have focused on the practical, real-world
application of VHDL.  This will not change.  The Steering Committee is
committed, however, to promoting a more active exchange of ideas and
experiences among the presenters, moderators and attendees through a
workshop and tutorial format.  Workshops will be informal, but highly
focused. Attendance to individual workshops will be limited in order
to facilitiate open discussion.

Workshop topics:

- Modeling Enhancements I: "Tweaks and Enhancements"

    The focus of this workshop will be the small "deficiencies" in
    VHDL that drive you nuts and make your job harder (e.g.  textio
    does not support all standard data types).  What language
    adjustments could (or should) be included in VHDL-200X to
    improve productivity?

- Modeling Enhancements II: "Challenges"

    The focus of this workshop will be the larger issues.  Given
    VHDL's existing capabilities, can we enhance or change these
    capabilities in VHDL-200X to meet future needs? Or, do we need
    more significant structural changes to make the designs of the
    future possible?

- VHDL at its limits: Switch-level and System-level Modeling

    Current usage trends of VHDL appear to favor RTL/synthesis
    coding.  VHDL is applicable to a broader spectrum of design
    challenges.  What VHDL techniques and capabilities facilitate
    modeling above and below the RTL level?

- Large Project Management & Control

    Design projects encompass more than writing and simulating HDLs.
    Systems on a chip and the increasing use of IP suggest the need
    for more stringent control; design database verification is also
    required.  How can these tasks be accomplished? Are there VHDL
    language changes that would better support these needs?

- Design and Synthesis for FPGAs

    Working with FPGAs begins to mimic the skills and techniques
    once used primarily in ASIC design. This implies that HDLs will
    become more prevalent in this process.  FPGA design also has
    some unique challenges.  Does VHDL usage enhance or inhibit
    these efforts?

- Design for Reuse: IP Modeling

    Some industry sources claim that verification requires up to 80%
    of a design effort. With design sizes increasing and cycle times
    decreasing, existing designs must be more efficiently
    re-utilized.  How?  What features of VHDL can be used to enhance
    design re-use?

- Testbenches and Testing

    As designs become more complex and verification time decreases,
    having more efficient and effective test methods is a must.
    VHDL is a powerful tool for this, especially through the use of
    testbenches.  Which VHDL techniques, methodologies, and tricks
    facilitate testing?

- VHDL vs. Verilog: Truths and Myths

    They share much in concept, but are significantly different. Are
    their uses different?  Is common evolution desirable, or should
    they each specialize?  Most efficient utilization, both together
    and separately?  Can they handle the design tasks of tomorrow?
    This workshop strives to highlight their uses, not accentuate
    the battles of the past.

In addition to the focused workshops, the Fall forum will offer a range
of tutorials (novice to expert level), and a few technical papers
pertaining to the practical applications of VHDL. Tutorials in support
of any of the above workshop topics are of interest.  Other potential
tutorial topics include (but are not limited to):

- Recent updates and new standards
- Behavi{*filter*}Synthesis
- Hardware/Software Co-design and Co-verification
- Reconfigurable logic and dynamically reprogrammable FPGAs
- Advanced use of VHDL
- Getting up to speed with VHDL

Potential topics for papers include (but are not limited to):

- System-on-a-Chip Design: Case Studies
- Design methodologies and flows
- Advanced use of VHDL
- Analog and Mixed-Signal Integration

Submission Guidelines

The VIUF Fall 1998 Steering Committee invites you to contribute your
considerable VHDL expertise for the benefit of other "power users" by
submitting an extended abstract for a workshop presentation (panels
welcome), tutorial and/or paper.  A workshop submission should identify
the above workshop topic under which it falls.

Submissions should include a 50-word abstract and a 500-1000 word
summary describing key ideas, results, major technical contributions,
advantages, limitations, application environment and/or directions for
future work, as appropriate.  Each abstract will undergo a thorough
review by an international panel of distinguished experts.  Those
submitting abstracts for workshops and tutorials will not be required to
prepare a full-length paper.  However, they will be required to provide
a copy of their slides in machine readable form by the Final Material
Submission Deadline.

Please send your abstract and summary information to the Program Chair,
Peter Ashenden, via regular mail (see sidebar) or via electronic mail
(preferred) at:


Submit your extended abstract by April 15, 1998.

Important Dates:

        Abstract Submission Deadline:           April 15, 1998
        Notification of Acceptance Sent:        May 25, 1998
        Final Material Submission Deadline:     July 31, 1998

Conference Chair                        Program Chair

Yvonne T. Ryan                          Peter J. Ashenden
Leader's Edge                           Dept. Computer Science
953 Mt Carmel Drive                     The University of Adelaide
San Jose, CA 95120                      Adelaide, SA 5005
USA                                     Australia
Phone: 408-997-6028                     Phone: +61 8 8303 4477
Fax:   408-997-7481                     Fax:   +61 8 8303 4366

Workshops Chair                         Tutorials Chair

James Goeke                             Jose Torres
Eastman Kodak Co.                       Viewlogic Systems, Inc.
901 Elmgrove Road                       47211 Lakeview Blvd
Rochester, NY 14653                     Fremont, CA 94538
USA                                     USA
Phone: 716-726-6571                     Phone: 510-659-0901
Fax:   716-726-7881                     Fax:   510-659-0129

Design Contest Chair                    Distributed Materials Chair

Mike McCollough                         Matt Hsu
Hughes Aircraft Co.                     Shomiti Systems, Inc.
PO Box 902, RS/R1/A508                  1800 Bering Drive
El Segundo, CA 90245                    San Jose, CA 95112
USA                                     USA
Phone: 310-334-7085                     Phone:
Fax:   310-334-1243                     Fax:

Publicity Co-chairs

Publicity Co-chairs

April Mitchell                          Nanette Collins
SEVA Technologies, Inc.                
9340 Carmel Mtn. Rd, Ste D              37 Symphony Road, Unit A
San Diego, CA 92129                     Boston, MA 02115
USA                                     USA
Phone: 619-538-6283                     Phone: 617-437-1822
Fax:   619-538-4271                     Fax:   617-425-0340

Forum Management

Conference Management Services (CMS)
528 Abrego Street, Suite 205
Monterey CA 93940
USA
Phone: 408-394-6384
Fax:   408-394-6382

Program Committee

Peter Ashenden - The University of Adelaide (Chair)
Matt Hsu - Shomiti Systems, Inc. (Distrib. Mat. Chair)

J. Bhasker - Lucent Technologies
Dennis Brophy - Mentor Graphics Corp.
Todd A. DeLong - The University of {*filter*}ia
Steve Drager - Air Force Research Laboratory
Wolfgang Ecker - Siemens Corporate Technology
Darrell Gibson - Bournemouth University
Bill Hanna - The Boeing Company
John Hillawi - DA Solutions
Michael McKinney - Texas Instruments, Inc.
Paul Menchini - Menchini & Associates
Gabe Moretti - Veribest, Inc.
Wolfgang Nebel - Universit?t Oldenburg
Serafin Olcoz - SIDSA
Greg Peterson - Air Force Research Laboratory
Mark Ronan - Northern Telecom Ltd.
Lance Thompson - IBM Corp.
John Willis - FTL Systems, Inc.
Philip Wilsey - The University of Cincinnati



Wed, 07 Jun 2000 03:00:00 GMT  
 
 [ 1 post ] 

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