There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand 
Author Message
 There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand

Help me please,
im using FPGA Advantage for HDL Designer Series (version 2001.5b (build
9)). release 5.2
ModelSim SE Version 5.5e

I put a counter in a block diagram... i run the simulation and if i press
run
i get this warning (but its an error)...

 ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the
result will be 'X'(es).
#    Time: 0 ns  Iteration: 0  Instance: /entry

How can i solve it!?

Thank you

Luigi L.



Mon, 09 Aug 2004 00:00:13 GMT  
 There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand
Seems like, you have two or more processes driving a single signal.
Would you please post more information or parts of your code?
Regards,
Steffen



Quote:

> Help me please,
> im using FPGA Advantage for HDL Designer Series (version 2001.5b (build
> 9)). release 5.2
> ModelSim SE Version 5.5e

> I put a counter in a block diagram... i run the simulation and if i press
> run
> i get this warning (but its an error)...

>  ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the
> result will be 'X'(es).
> #    Time: 0 ns  Iteration: 0  Instance: /entry

> How can i solve it!?

> Thank you

> Luigi L.



Mon, 09 Aug 2004 01:37:51 GMT  
 There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand

Quote:
> Seems like, you have two or more processes driving a single signal.

Lets say we have two blocks  (clocked), a counter and another
custom-block...
the problem rises when i give the same wire-name to the two clocks....
one block (counter) come from modulware lib. the other is mine.

The counter works correctly, but the warning message remains....

bye
Luigi.



Mon, 09 Aug 2004 02:30:51 GMT  
 There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand

Quote:
> Lets say we have two blocks  (clocked), a counter and another
> custom-block...
> the problem rises when i give the same wire-name to the two clocks....
> one block (counter) come from modulware lib. the other is mine.

> The counter works correctly, but the warning message remains....

Ah!
I didnt write code, i used all predefinited components, and i generate the
clock with the clock command in the simulator.

Ciao
Luigi.



Mon, 09 Aug 2004 02:33:52 GMT  
 There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand
[TOFU corrected]

Quote:


>>  ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,
>>  the
>> result will be 'X'(es).
>> #    Time: 0 ns  Iteration: 0  Instance: /entry
> Seems like, you have two or more processes driving a single signal.
> Would you please post more information or parts of your code?

Normaly this message means, the same, as modelsim writes on the screen.
In time 0 ns all (most) signals are U. So are the operands of an arithmetic
function. This message said, that whenever you add, subtract or similar,
with U the result will be X.

To resolve this problem, you could initialise all Signals in the signal
declaration part.

bye Thomas

--
Thomas Stanka TE/EMD4
Space Communications Systems
Tesat Spacecom GmbH & Co KG



Mon, 09 Aug 2004 15:46:26 GMT  
 There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand


Quote:

>Help me please,
>im using FPGA Advantage for HDL Designer Series (version 2001.5b (build
>9)). release 5.2
>ModelSim SE Version 5.5e

>I put a counter in a block diagram... i run the simulation and if i press
>run
>i get this warning (but its an error)...

> ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the
>result will be 'X'(es).
>#    Time: 0 ns  Iteration: 0  Instance: /entry

>How can i solve it!?

>Thank you

>Luigi L.

This occurs when a numeric function is called from e.g. the numeric_std
library. For instance, there is a function

to_integer

which takes an argument of vector "unsigned". If this vector contains
values other than '1' or '0' this will cause the warning message you see
above. This is quite common at time 0 ns because all signals that are of
type unsigned, signed, std_logic_vector will contain 'U'
(uninitialized).

What can you do?

a) if you understand the operation of your circuit, and you are
confident that the function is correct, just ignore the warning.

b) if you understand the operation of your circuit, and you are
confident that the function is correct, you can also get Modelsim to
disable the warning. I only know how to do this when running Modelsim
standalone, I don't know how to do it in FPGA Advantage. In stand alone
Modelsim, go to Options -> Compile and then in the "suppress warnings"
part of the dialogue, check

"From IEEE Numeric Std Packages"

assuming you are using Numeric std.

c) you could initialise signals. However I would not recommend this as
initialisation values are ignored for synthesis, and so you might hide a
functional error.

My preferred option is a), i.e just ignore the warnings as they are
occurring at 0 ns.

If you see warnings later in time (after 0 ns), then you need to worry
as something is not working in your design.

regards

Alan

--
Alan Fitch
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom

Fax: +44 1425 471573                             Web: http://www.doulos.com

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Tue, 10 Aug 2004 17:30:43 GMT  
 
 [ 6 post ] 

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