State Machine - State Definition Question 
Author Message
 State Machine - State Definition Question

Hello,

I have started to work with state machines and I have some questions
that I am not able to find in books.

What is the definition of a state?  
When creating a state diagram how should I pick the states?

Thanks
Rob



Sun, 10 Apr 2005 08:09:28 GMT  
 State Machine - State Definition Question
Rob,

You are really talking about a Finite State Machine.  It is a set of
logic that can be in only a certain number of states, a finite number.

In creating a state diagram, pick states that make sense to you in your
design, labeling them as such.  Draw and label the arrows that will show
what conditions keep the machine in one state or transfer to another.  I
like to put in the circles the signals that are asserted in a given
state.

Sometimes, when learning this process,  a table of states is more
useful.  Make 3 columns, present state, inputs and next state.

Any good text on logic design should cover this.  Many texts on VHDL
cover it as well, just be mindful of the notation involved.

Good luck.

Clyde

Quote:

> Hello,

> I have started to work with state machines and I have some questions
> that I am not able to find in books.

> What is the definition of a state?
> When creating a state diagram how should I pick the states?

> Thanks
> Rob



Sun, 10 Apr 2005 09:41:59 GMT  
 State Machine - State Definition Question
Your library must be very limited not to have anything on FSM's. Anyway, I
used the following words in google, and got some okay links:

fsm finite state machine example explained

regards,
juza



Sun, 10 Apr 2005 15:45:13 GMT  
 State Machine - State Definition Question
Hi Rob,

This is a good reference to get you started:
http://fanying2.fanying.com/contemporary_logic_design/chapter8/chapte...

Jon Parker


Quote:
> Rob,

> You are really talking about a Finite State Machine.  It is a set of
> logic that can be in only a certain number of states, a finite number.

> In creating a state diagram, pick states that make sense to you in your
> design, labeling them as such.  Draw and label the arrows that will show
> what conditions keep the machine in one state or transfer to another.  I
> like to put in the circles the signals that are asserted in a given
> state.

> Sometimes, when learning this process,  a table of states is more
> useful.  Make 3 columns, present state, inputs and next state.

> Any good text on logic design should cover this.  Many texts on VHDL
> cover it as well, just be mindful of the notation involved.

> Good luck.

> Clyde


> > Hello,

> > I have started to work with state machines and I have some questions
> > that I am not able to find in books.

> > What is the definition of a state?
> > When creating a state diagram how should I pick the states?

> > Thanks
> > Rob



Sun, 10 Apr 2005 21:08:43 GMT  
 State Machine - State Definition Question
Thank you Clyde for your help.

What I am looking for is how do I decide the states that make sense?  

In a state is there a rule of thumb that says you should keep it to so
many clock cycles before I make a new state?  Or if a state has so
much in it should it become a FSM on its own or broken out into a few
more states?

What is the deciding factor to make a state a state and not a response
in a state.

I understand the mechanics for a FSM in a classroom setting.  My
problem is bringing that knowledge to read world work.

Thanks,
Rob


Quote:
> Rob,

> You are really talking about a Finite State Machine.  It is a set of
> logic that can be in only a certain number of states, a finite number.

> In creating a state diagram, pick states that make sense to you in your
> design, labeling them as such.  Draw and label the arrows that will show
> what conditions keep the machine in one state or transfer to another.  I
> like to put in the circles the signals that are asserted in a given
> state.

> Sometimes, when learning this process,  a table of states is more
> useful.  Make 3 columns, present state, inputs and next state.

> Any good text on logic design should cover this.  Many texts on VHDL
> cover it as well, just be mindful of the notation involved.

> Good luck.

> Clyde


> > Hello,

> > I have started to work with state machines and I have some questions
> > that I am not able to find in books.

> > What is the definition of a state?
> > When creating a state diagram how should I pick the states?

> > Thanks
> > Rob



Sun, 10 Apr 2005 21:17:26 GMT  
 State Machine - State Definition Question
Hi Rob!

Quote:
> What I am looking for is how do I decide the states that make sense?  

> In a state is there a rule of thumb that says you should keep it to so
> many clock cycles before I make a new state?  Or if a state has so
> much in it should it become a FSM on its own or broken out into a few
> more states?

> What is the deciding factor to make a state a state and not a response
> in a state.

You talk about state machines without an application.

Assume, you got an sequential algorithm. In this algorithm some things
have been done first, other things after the first ones and at last you
have to do some third things.
In other words: Your algorithm can be computed in 3 steps.

These steps are the states of the state machine.

Depending on your algorithm it is clear, what a state is and how long it
should take (until the results of each step have been computed).

_Iff_ you are able to split these 3 states into e.g. 10 states, if you
break the steps into some sub-steps, you can rewrite your state machine
and you can build a new one with 10 states. -> It depends on the count
of the sequential steps, if a state can be called a state.

Because the each of the 10 steps is smaller that one of the original 3
steps, your state machine may be clocked faster.

Did I understand your question right?

Ralf



Sun, 10 Apr 2005 22:48:30 GMT  
 State Machine - State Definition Question

Quote:

> In a state is there a rule of thumb that says you should keep it to so
> many clock cycles before I make a new state?  Or if a state has so
> much in it should it become a FSM on its own or broken out into a few
> more states?

It's a trade-off of speed, gates and design time.
If state cases have other mode or input subcases,
then you use more gates and timing margin.
If you use more state cases, then it takes
more ticks to get something done, but timing is easier.

Quote:
> What is the deciding factor to make a state a state and not a response
> in a state.

If you mean "when do you need a wait state, you have to look at the
output timing requirements.

Quote:
> I understand the mechanics for a FSM in a classroom setting.  My
> problem is bringing that knowledge to read world work.

Consider closing the text book and learning an HDL and a simulator.
You need a quick code-edit to waveform redisplay to really
understand controllers.

Classical FSM design methods came from a time when gates
came four to package and were hand fitted by schematic only.

  -- Mike Treseler



Mon, 11 Apr 2005 01:46:46 GMT  
 State Machine - State Definition Question
Thank you to everyone who helped.  
I have a better understanding about FSMs.

Thanks again,
Rob



Mon, 11 Apr 2005 22:20:35 GMT  
 
 [ 8 post ] 

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