wait statement 
Author Message
 wait statement

Hi,
 Iam new to VHDL . Iam using evaluation version of max plus and
leonardo spectrum. Iam trying to implement a process with multiple
wait statements. When i use multiple wait statements in my process,
and synthesize it, the leonardo specturm reports
---
Error, multiple wait statements do not specify the same clock;
---
Whats does the error correspond?? Is it that we cant use multiple wait
statements with VHDL [but i say many postings with multiple wait]
(or) Is my evaluation version of synthesis tool preventing me to
synthesize??

My goal is when the process executes first time, the signal RSTEN
should be 0 for 100ns and when the process resumes, the RSTEN will
become '1' and will be permanently suspended..

                RSTEN <= '0';
                wait for 100ns;
                RSTEN <= '1';
                wait;  

My need for this is if i use counting logics, the synthesizer is not
fitting the design (MAX7032),demands for extra 11 gates .Please post
your valuable feedbacks
Regards
Senthil



Mon, 07 Feb 2005 16:44:43 GMT  
 wait statement
Quote:
> Iam new to VHDL . Iam using evaluation version of max plus and
>leonardo spectrum. Iam trying to implement a process with multiple
>wait statements.

BEN: MaxPlus and Leonardo are synthesis tools, and you must abide by the
synthesis rules, which are a restricted subset of the VHDL language.

Quote:
> When i use multiple wait statements in my process,
>and synthesize it, the leonardo specturm reports
>---
>Error, multiple wait statements do not specify the same clock;
>---
>Whats does the error correspond??

BEN: The "wait for" and multiple "wait until" are not supported in synthesis.

Quote:
> Is it that we cant use multiple wait
>statements with VHDL [but i say many postings with multiple wait]
>(or) Is my evaluation version of synthesis tool preventing me to
>synthesize??

>My goal is when the process executes first time, the signal RSTEN
>should be 0 for 100ns and when the process resumes, the RSTEN will
>become '1' and will be permanently suspended..

>            RSTEN <= '0';
>            wait for 100ns;
>            RSTEN <= '1';
>            wait;  

>My need for this is if i use counting logics, the synthesizer is not
>fitting the design (MAX7032),demands for extra 11 gates .Please post
>your valuable feedbacks

BEN: You must use a synchronous counter to determine the time out period.
Can you have the reset be defined thru an anlog circuit outside your design?
---------------------------------------------------------------------------
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Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
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* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------


Tue, 08 Feb 2005 00:06:17 GMT  
 wait statement
Wait statement can only appear in a process in one form. You can use
many "wait for 10 ns" or "wait on clk"  in one process, but  you can
not combine the two.
I always write the reset statement like below:
reset <= '0', '1' after 100 ns, '0' after 1000 ns....................;


Fri, 11 Feb 2005 15:32:52 GMT  
 wait statement
Hi .. "ferry"!

Quote:
> I always write the reset statement like below:
> reset <= '0', '1' after 100 ns, '0' after 1000 ns....................;

O.k., this suits well for testbenches, but this is not supported by
synthesis. (Ths original poster wants to synthesize the code!)

Ralf



Fri, 11 Feb 2005 15:49:40 GMT  
 wait statement
for synthesis, you can only use either the implied  wait (sensitivity
list) or wait until clk=''.  For testbenches, you can use any combination
of waits.  There is nothing wrong with using both wait until x and wait
for n ns in the same process in a testbench.

Quote:

> Wait statement can only appear in a process in one form. You can use
> many "wait for 10 ns" or "wait on clk"  in one process, but  you can
> not combine the two.
> I always write the reset statement like below:
> reset <= '0', '1' after 100 ns, '0' after 1000 ns....................;

--
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President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950

http://www.andraka.com

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  temporary safety deserve neither liberty nor safety."
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Fri, 11 Feb 2005 20:58:30 GMT  
 
 [ 5 post ] 

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