relational operators 
Author Message
 relational operators

Page 7-4 of the std_1076_1987 VHDL LRM indicates that "=" and "/=" are defined
for all types, both pre-defined and user-defined.
It goes on to say that the ordering operators are defined for any scalar type
and for 1 dimensional arrays whose elements are discrete types.

This would imply, that for STD_LOGIC_VECTOR, = /= > < <= >= are all implicitly
defined by the language.

1) Is the above statement correct?

2) Can implicitly defined functions be redefined by the user? Page 2-6 implies
   that it is illegal VHDL to have two functions that have exactly the same
   name, paramaters and return types.

3) The SYNOPSYS packages STD_LOGIC_ARITH and STD_LOGIC_UNSIGNED define
   relational operators for all their defined types including STD_LOGIC
   and STD_LOGIC_VECTOR.
   I heard a rumour from another VHDL vendor that synopsys have recognised
   that these packages are "erroneous" and will remove these functions from
   the packages.  Can anyone comment on this?

Andrew Hana
Hewlett Packard
Bristol, England.



Tue, 30 Jan 1996 15:42:13 GMT  
 relational operators

Quote:

>Page 7-4 of the std_1076_1987 VHDL LRM indicates that "=" and "/=" are defined
>for all types, both pre-defined and user-defined.

Almost true; they are not defined for access and file types.  But they are for
*all* others.

Quote:
>It goes on to say that the ordering operators are defined for any scalar type
>and for 1 dimensional arrays whose elements are discrete types.

Quite true.

Quote:
>This would imply, that for STD_LOGIC_VECTOR, = /= > < <= >= are all implicitly
>defined by the language.

Also true.

Quote:
>1) Is the above statement correct?

See above.

Quote:
>2) Can implicitly defined functions be redefined by the user? Page 2-6 implies
>   that it is illegal VHDL to have two functions that have exactly the same
>   name, paramaters and return types.

Yes to the question; I think you've misread Page 2-6.  If a user-defined
function that is a homograph of a predefined operator is declared in the same
declarative region as the predefined operator, then the user-defined function
hides the predefined operator in the remainder of the declarative region.

However, you can't take advantage of this rule without modifying the package
std_logic_1164.  You could write another package with the desired forms of
your operators in them, but then you have to be careful with use clauses.
(Expanded names allow you to select which function you want.)

Quote:
>   I heard a rumour from another VHDL vendor that synopsys have recognised
>   that these packages are "erroneous" and will remove these functions from
>   the packages.  Can anyone comment on this?

I've not heard this.  As I'm a member of both the language maintainence team
and the 92 design team, I suspect that I would have if it were officially
raised as a point.

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Tue, 30 Jan 1996 22:15:41 GMT  
 
 [ 2 post ] 

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