VHDL-93 generates different concatenation results from VHDL-87 
Author Message
 VHDL-93 generates different concatenation results from VHDL-87

I get the warning message of the subject from Synopsys Design Compiler
synthesis program. Its meaning is described in the FAQ, but I can't think of
any simple way to get rid of the bothering warning message.

Here's one example where I get the warning:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity SUB26 is
        port (
                A: in std_ulogic_vector(25 downto 0);   -- Max 26 bits,treated as signed number
                B: in std_ulogic_vector(25 downto 0);   -- Max 26 bits,treated as signed number
                R: out std_ulogic_vector(25 downto 0);  -- R = A-B
                C: out std_ulogic                       -- 1, if A<B(compared as signed numbers)
        );
end;
architecture RTL of SUB26 is begin
        -- Total cell area: 1943.4
        -- Critical path time: 4.27
        process(A,B)
                variable a2,b2,r2 : signed(26 downto 0);
        begin
                a2 := signed(A(25) & A);   --<-- this line gives the warning
                b2 := signed(B(25) & B);   --<-- this too
                r2 := a2-b2;
                C <= r2(26);
                R <= std_ulogic_vector(r2(25 downto 0));
        end process;
end;

I guess the bounds of A(25) & A become (25 downto -1) in VHDL-87, which is
wrong (but not a problem since I use -93). I think the problem would go away
if I'd break the assignment on two lines, but I'd like to keep my code
terse.



Sun, 15 May 2005 21:36:17 GMT  
 VHDL-93 generates different concatenation results from VHDL-87
Replace:
a2 := signed(A(25) & A);

with:
a2 := resize(signed(A),27);

('resize' is part of numeric_std)
The same for b2.

Egbert Molenkamp



Quote:
> I get the warning message of the subject from Synopsys Design Compiler
> synthesis program. Its meaning is described in the FAQ, but I can't think
of
> any simple way to get rid of the bothering warning message.

> Here's one example where I get the warning:

> library IEEE;
> use IEEE.STD_LOGIC_1164.all;
> use IEEE.NUMERIC_STD.all;
> entity SUB26 is
> port (
> A: in std_ulogic_vector(25 downto 0); -- Max 26 bits,treated as signed
number
> B: in std_ulogic_vector(25 downto 0); -- Max 26 bits,treated as signed
number
> R: out std_ulogic_vector(25 downto 0); -- R = A-B
> C: out std_ulogic -- 1, if A<B(compared as signed numbers)
> );
> end;
> architecture RTL of SUB26 is begin
> -- Total cell area: 1943.4
> -- Critical path time: 4.27
> process(A,B)
> variable a2,b2,r2 : signed(26 downto 0);
> begin
> a2 := signed(A(25) & A);   --<-- this line gives the warning
> b2 := signed(B(25) & B);   --<-- this too
> r2 := a2-b2;
> C <= r2(26);
> R <= std_ulogic_vector(r2(25 downto 0));
> end process;
> end;

> I guess the bounds of A(25) & A become (25 downto -1) in VHDL-87, which is
> wrong (but not a problem since I use -93). I think the problem would go
away
> if I'd break the assignment on two lines, but I'd like to keep my code
> terse.



Sun, 15 May 2005 23:25:17 GMT  
 VHDL-93 generates different concatenation results from VHDL-87

Quote:

> Replace:
> a2 := signed(A(25) & A);

> with:
> a2 := resize(signed(A),27);

Thanks, looks like it works. What if I'm not just doing a simple sign
extension, but something like this:

        signal s : std_ulogic_vector(21 downto 0);
        signal r : std_ulogic_vector(21 downto 0);
        signal c : std_ulogic_vector(7 downto 0);
        signal bin1,bin2 : unsigned(8 downto 0);
...
        bin1 <= unsigned(r(0) & s(0) & s(21 downto 16) & c(0));

I really don't want to break this into multiple lines.



Mon, 16 May 2005 22:57:59 GMT  
 VHDL-93 generates different concatenation results from VHDL-87
As you already read in the FAQ
http://www.vhdl.org/vi/comp.lang.vhdl/FAQ1.html#concat

the problem is solved in the VHDL'93 (almost then years ago!).
So I would first ask the tool vendor when it will support it.

The tooling I use support VHDL'93 so I have no problems.
But maybe the following trick helps you in the meantime.
I made function that converts a vector into an ascending one
using to_ascending.
I'm curious to hear if this solves your problem ?

Best regards
Egbert Molenkamp

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conc is
  port (p,q : in std_logic_vector(3 downto 0);
        ps, qs : in signed(3 downto 0);
        b : in std_logic;
        r : out std_logic_vector(7 downto 0);
    s : out std_logic_vector(4 downto 0);
    rs : out signed( 7 downto 0));
end conc;

  ARCHITECTURE test OF conc IS
    function to_ascending(inp : std_logic) return std_logic_vector is
    variable tmp : std_logic_vector(0 to 0);
  begin
  tmp := ""&inp;
  return tmp;
  end to_ascending;

  function to_ascending(inp : std_logic_vector) return std_logic_vector is
    variable tmp : std_logic_vector(0 to inp'length-1);
  begin
   tmp := inp;
   return tmp;
  end to_ascending;

  function to_ascending(inp : signed) return signed is
  begin
    return signed(to_ascending(std_logic_vector(inp)));
  end to_ascending;

  BEGIN
   r <= to_ascending(p) & q;
 s <= to_ascending(b) & q;

 rs <= to_ascending(ps) & qs;

  end test;



Quote:

> > Replace:
> > a2 := signed(A(25) & A);

> > with:
> > a2 := resize(signed(A),27);

> Thanks, looks like it works. What if I'm not just doing a simple sign
> extension, but something like this:

> signal s : std_ulogic_vector(21 downto 0);
> signal r : std_ulogic_vector(21 downto 0);
> signal c : std_ulogic_vector(7 downto 0);
> signal bin1,bin2 : unsigned(8 downto 0);
> ...
> bin1 <= unsigned(r(0) & s(0) & s(21 downto 16) & c(0));

> I really don't want to break this into multiple lines.



Tue, 17 May 2005 02:42:23 GMT  
 VHDL-93 generates different concatenation results from VHDL-87

Quote:

> the problem is solved in the VHDL'93 (almost then years ago!).
> So I would first ask the tool vendor when it will support it.

Yes they do--but the tool gives a big bold warning each time. And there are
so many of these useless warnings, that real problems bury under them. Not
nice. I can't find any option to disable that warning, either.

Quote:
> I made function that converts a vector into an ascending one
> using to_ascending.
> I'm curious to hear if this solves your problem ?

Thanks--it did after fixes. First the synthesis program complained that
"error: empty string constants are not supported for synthesis". I fixed
that. Then I found out that if I assign ascending vector to a descending
vector with the "<=" operator, it still gives the warning. So the final
solution is:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity CONC is
        port (
                P, Q   : in std_logic_vector(3 downto 0);
                PS, QS : in signed(3 downto 0);
                B      : in std_logic;
                R      : out std_logic_vector(7 downto 0);
                S      : out std_logic_vector(4 downto 0);
                RS     : out signed(7 downto 0)
        );
end;

architecture TEST of CONC is
        function to_ascending(INP: std_logic) return std_logic_vector is
                variable tmp: std_logic_vector(0 to 0);
        begin
                tmp(0) := INP;
                return tmp;
        end;

        function to_ascending(INP: std_logic_vector) return std_logic_vector is
                variable tmp: std_logic_vector(0 to inp'length-1);
        begin
                tmp := INP;
                return tmp;
        end;

        function to_ascending(INP: signed) return signed is
        begin
                return signed(to_ascending(std_logic_vector(INP)));
        end;

        function to_descending(INP: std_logic_vector) return std_logic_vector is
                variable tmp: std_logic_vector(inp'length-1 downto 0);
        begin
                tmp := INP;
                return tmp;
        end;
begin
        R  <= to_descending(to_ascending(P) & Q); --no warning
        S  <= to_descending(to_ascending(B) & Q); --no warning
        RS <= to_ascending(PS) & to_ascending(QS); --gives warning
end;



Tue, 17 May 2005 18:50:16 GMT  
 VHDL-93 generates different concatenation results from VHDL-87



Quote:

> > the problem is solved in the VHDL'93 (almost then years ago!).
> > So I would first ask the tool vendor when it will support it.

> Yes they do--but the tool gives a big bold warning each time. And there
are
> so many of these useless warnings, that real problems bury under them. Not
> nice. I can't find any option to disable that warning, either.

> > I made function that converts a vector into an ascending one
> > using to_ascending.
> > I'm curious to hear if this solves your problem ?

> Thanks--it did after fixes. First the synthesis program complained that
> "error: empty string constants are not supported for synthesis". I fixed
> that. Then I found out that if I assign ascending vector to a descending
> vector with the "<=" operator, it still gives the warning. So the final
> solution is:

Mmmm .. maybe the software people who implemented the synthesis
tool should first have a real VHDL training.

Of course I can imagine why a tool generate useless warnings. A tool vendor
thinks that a VHDL designer thinks that assigning an ascending vector to a
descending vector will perform a bit reversal. However to many useless
warning will
result in not reading them anymore .. and a real warning is missed!

I checked my previous solution (with 'to_ascending' function) with Leonardo
Spectrum (Mentor).
It resulted in a correct circuit without warnings.

Egbert Molenkamp



Tue, 17 May 2005 20:38:44 GMT  
 VHDL-93 generates different concatenation results from VHDL-87



Quote:


> > the problem is solved in the VHDL'93 (almost then years ago!).
> > So I would first ask the tool vendor when it will support it.

> Yes they do--but the tool gives a big bold warning each time.
And there are
> so many of these useless warnings, that real problems bury under
them. Not
> nice. I can't find any option to disable that warning, either.

<snip>

I don't know if this will help, but if you look at Solvnet article

http://solvnet.synopsys.com/retrieve/901801.html

it says you can set a variable

hdlin_vhdl93_concat

to false to force the VHDL 87 interpretation, which I guess might
get rid of the warnings?? I haven't tried it though.

regards

Alan
--
Alan Fitch
[HDL Consultant]

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Tue, 17 May 2005 22:30:42 GMT  
 
 [ 7 post ] 

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