VHDL-93 generates different concatenation results from VHDL-87

Quote:

> the problem is solved in the VHDL'93 (almost then years ago!).

> So I would first ask the tool vendor when it will support it.

Yes they do--but the tool gives a big bold warning each time. And there are

so many of these useless warnings, that real problems bury under them. Not

nice. I can't find any option to disable that warning, either.

Quote:

> I made function that converts a vector into an ascending one

> using to_ascending.

> I'm curious to hear if this solves your problem ?

Thanks--it did after fixes. First the synthesis program complained that

"error: empty string constants are not supported for synthesis". I fixed

that. Then I found out that if I assign ascending vector to a descending

vector with the "<=" operator, it still gives the warning. So the final

solution is:

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.NUMERIC_STD.all;

entity CONC is

port (

P, Q : in std_logic_vector(3 downto 0);

PS, QS : in signed(3 downto 0);

B : in std_logic;

R : out std_logic_vector(7 downto 0);

S : out std_logic_vector(4 downto 0);

RS : out signed(7 downto 0)

);

end;

architecture TEST of CONC is

function to_ascending(INP: std_logic) return std_logic_vector is

variable tmp: std_logic_vector(0 to 0);

begin

tmp(0) := INP;

return tmp;

end;

function to_ascending(INP: std_logic_vector) return std_logic_vector is

variable tmp: std_logic_vector(0 to inp'length-1);

begin

tmp := INP;

return tmp;

end;

function to_ascending(INP: signed) return signed is

begin

return signed(to_ascending(std_logic_vector(INP)));

end;

function to_descending(INP: std_logic_vector) return std_logic_vector is

variable tmp: std_logic_vector(inp'length-1 downto 0);

begin

tmp := INP;

return tmp;

end;

begin

R <= to_descending(to_ascending(P) & Q); --no warning

S <= to_descending(to_ascending(B) & Q); --no warning

RS <= to_ascending(PS) & to_ascending(QS); --gives warning

end;