Creating a clock with a clock enable 
Author Message
 Creating a clock with a clock enable

Hi.

I was trying to write some VHDL code to generate a new clock based on
another clock and a clock enable (CE) control pin.  The goal of my
design is to output a clock pulse that is the same frequency as the
input clock but would be zero if the CE would be zero. When the CE is
one, then the generated clock should look exactly like the original
input clock. Ideally, I would like the clocks to be exactly
synchronized, but I can live with a delay of one clock period.

I guess this problem is similar to having a 2 input AND gate, whose one
input accepts the original clock and the other input accepts the CE
signal.

I have tried to use the input clock (clk) that I am using in the
"if (clk'event and clk='1') then..." statement as an input to an and
gate, but Synopsys doesn't like this syntax at all and generates an
error.

I have also tried using variables, but this method only outputs a single
pulse that is high when CE='1' and low when CE='0', but there are no
transitions.  I'm attaching a part of my code for anyone who has dealt
with such control signals.

Any help would be greatly appreciated.

Thanks in advance.

Nestor Caouras

http://www.*-*-*.com/ ~nestor/addr.html
|-------------------------------------------|
| Dept. of Electrical and Computer Eng.     |
| Concordia University                      |
| 1455 de Maisonneuve Blvd (West)           |
| Montreal, Quebec, Canada H3G 1M8.         |
| Tel: (514)848-8784    Fax: (514)848-2802  |
|-------------------------------------------|

[ arctan_control2_temp.vhdl 1K ]
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;

entity arctan_control2 is
  port( ready, slowclk, reset: in std_logic;
        clkout : out std_logic);
end arctan_control2;

-- slowclk is the original input clock operating at frequency Fz MHz
-- ready is a signal that determines the value of the clock enable (CE)
--   input used for the generated output clock "clkout"

architecture behv of arctan_control2 is
signal ready_old : std_logic;
signal clk_net : std_logic;

begin

  clk_net <= slowclk;

  control: process (slowclk,ready,reset)
    variable valid  : boolean;
    variable cnt : std_logic_vector(2 downto 0);
    variable CE : std_logic;
    variable clk_tmp : std_logic;

  begin
    if (reset = '1') then

       ...

    elsif (slowclk'event and slowclk='1') then
      clk_tmp := '1';   -- this could be changed or removed depending
      if (ready_old = '0' and ready = '1') then -- if a rising edge transition was
                                                -- detected from previous value of "ready"
                                                -- to current value of "ready", then set
                                                -- "valid" flag to TRUE
        valid := true;
        cnt := "000"; -- initialize the counter to zero
      end if;

      if valid then
        if cnt < 6 then              -- count for 6 clock cycles and keep
          cnt := cnt + 1;       -- CE high
          CE := '1';
        else
          cnt := "000";               -- the max count was reached and CE is
          CE := '0';            -- set back to low.
          valid := false;       -- control flag "valid" also reset
        end if;
      end if;

      ready_old <= ready;    -- store the current value of ready for
                                -- use in the next cycle
      clkout <= clk_tmp and CE;      -- generate the output clock

    end if;

  end process;

end behv;



Tue, 17 Oct 2000 03:00:00 GMT  
 Creating a clock with a clock enable



Quote:
> Hi.

> I was trying to write some VHDL code to generate a new clock based on
> another clock and a clock enable (CE) control pin.  The goal of my
> design is to output a clock pulse that is the same frequency as the
> input clock but would be zero if the CE would be zero. When the CE is
> one, then the generated clock should look exactly like the original
> input clock. Ideally, I would like the clocks to be exactly
> synchronized, but I can live with a delay of one clock period.

> I guess this problem is similar to having a 2 input AND gate, whose one
> input accepts the original clock and the other input accepts the CE
> signal.

> I have tried to use the input clock (clk) that I am using in the
> "if (clk'event and clk='1') then..." statement as an input to an and
> gate, but Synopsys doesn't like this syntax at all and generates an
> error.

> I have also tried using variables, but this method only outputs a single
> pulse that is high when CE='1' and low when CE='0', but there are no
> transitions.  I'm attaching a part of my code for anyone who has dealt
> with such control signals.

> Any help would be greatly appreciated.

> Thanks in advance.

> Nestor Caouras

> http://www.ece.concordia.ca/~nestor/addr.html
> |-------------------------------------------|
> | Dept. of Electrical and Computer Eng.     |
> | Concordia University                      |
> | 1455 de Maisonneuve Blvd (West)           |
> | Montreal, Quebec, Canada H3G 1M8.         |
> | Tel: (514)848-8784    Fax: (514)848-2802  |
> |-------------------------------------------|
> library IEEE;
> use IEEE.STD_LOGIC_1164.all;
> use IEEE.std_logic_unsigned.all;

> entity arctan_control2 is
>   port( ready, slowclk, reset: in std_logic;
>    clkout : out std_logic);
> end arctan_control2;

> -- slowclk is the original input clock operating at frequency Fz MHz
> -- ready is a signal that determines the value of the clock enable (CE)
> --   input used for the generated output clock "clkout"

> architecture behv of arctan_control2 is
> signal ready_old : std_logic;
> signal clk_net : std_logic;

> begin

>   clk_net <= slowclk;

>   control: process (slowclk,ready,reset)
>     variable valid  : boolean;
>     variable cnt : std_logic_vector(2 downto 0);
>     variable CE : std_logic;
>     variable clk_tmp : std_logic;

>   begin
>     if (reset = '1') then

>        ...

>     elsif (slowclk'event and slowclk='1') then
>       clk_tmp := '1';      -- this could be changed or removed depending
>       if (ready_old = '0' and ready = '1') then    -- if a rising edge
transition was
>                                            -- detected from previous value of "ready"
>                                            -- to current value of "ready", then set
>                                            -- "valid" flag to TRUE
>         valid := true;
>         cnt := "000";    -- initialize the counter to zero
>       end if;

>       if valid then
>         if cnt < 6 then         -- count for 6 clock cycles and keep
>      cnt := cnt + 1;       -- CE high
>      CE := '1';
>    else
>      cnt := "000";               -- the max count was reached and CE is
>      CE := '0';            -- set back to low.
>      valid := false;       -- control flag "valid" also reset
>    end if;
>       end if;

>       ready_old <= ready;       -- store the current value of ready for
>                            -- use in the next cycle
>       clkout <= clk_tmp and CE; -- generate the output clock

>     end if;

>   end process;

> end behv;

Forget about clk_tmp.  You want clkout <= slowclk and CE;  I don't like that
this statement is inside of an IF that only gets evaluated on rising clock
edges.  That is probably what Synopsys is complaining about.  Bring CE (or a
signal copy of it) out of this process and make the clkout <= slowclk and CE;
statement its own process.

--
Rich Iachetta
IBM Corporation



Fri, 20 Oct 2000 03:00:00 GMT  
 Creating a clock with a clock enable

Thanks for the tip. I'm still pretty new to VHDL.

Nestor



Thu, 26 Oct 2000 03:00:00 GMT  
 
 [ 3 post ] 

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