FPGA to ASIC conversion 
Author Message
 FPGA to ASIC conversion

Dear all,

Does anyone know how to make/steps conversion from FPGA gate-level
netlist to ASIC gate-level netlist ?

I'm currently triying convert Xilinx FPGA to ASIC's CMOS Technology by
using Synopsys Design Compiler.
But, some instance was unresolved references such OBUF , DFF ( flip-
flop )!!
Could anyone share your experiences with me ?

Thanks.

regrads,
henry

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http://www.*-*-*.com/



Wed, 04 Jun 2003 11:18:05 GMT  
 FPGA to ASIC conversion
If you have a gate level netlist, how do you get it into Design Compiler?
If you are at gate level then the usually the ASIC vendor has a conversion
or you must manually convert.  If you are using Xilinx are you using it to
generate a VHDL netlist after place and route?  The netlist generated should
easily translate as long as you include the correct library.

Walt

Quote:

> Dear all,

> Does anyone know how to make/steps conversion from FPGA gate-level
> netlist to ASIC gate-level netlist ?

> I'm currently triying convert Xilinx FPGA to ASIC's CMOS Technology by
> using Synopsys Design Compiler.
> But, some instance was unresolved references such OBUF , DFF ( flip-
> flop )!!
> Could anyone share your experiences with me ?

> Thanks.

> regrads,
> henry

> Sent via Deja.com
> http://www.deja.com/



Fri, 06 Jun 2003 13:07:30 GMT  
 FPGA to ASIC conversion
Hi Henri
You could do your retargeting with leonardo tool from Exemplar, this
synthesizer is able to do that. this one is able to read a vhdl gate
level net list, transforms this one on a generic design and after that
you could do a remaping on your ASIC technologies. That is the simplest
way, but owne condition is your ASIC library is supported by Leonardo.
If you haven't leonardo or this one doesn't support Asic Library, you
could rewrite your Vhdl gate level net list by supressing all specific
library calling and write in generic functionality each component
called by design.
If you want more details, feel free to contact me.
Jean-Eric LEROY


Quote:

> Dear all,

> Does anyone know how to make/steps conversion from FPGA gate-level
> netlist to ASIC gate-level netlist ?

> I'm currently triying convert Xilinx FPGA to ASIC's CMOS Technology by
> using Synopsys Design Compiler.
> But, some instance was unresolved references such OBUF , DFF ( flip-
> flop )!!
> Could anyone share your experiences with me ?

> Thanks.

> regrads,
> henry

> Sent via Deja.com
> http://www.deja.com/

Sent via Deja.com
http://www.deja.com/


Tue, 10 Jun 2003 16:58:25 GMT  
 
 [ 3 post ] 

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