Verilog-VHDL conversion - simulation semantics 
Author Message
 Verilog-VHDL conversion - simulation semantics

Hi,

I'm trying to convert an existing Verilog design
to a VHDL design.

The methodology I'm following is as follows.
All "regs" in Verilog become "variables" in VHDL,
and all "wires" become "signals".

However, I've a problem here. Verilog allows
declaration of "regs" at the "module" level,
that is outside an "always" block. These "regs"
can be used in all the always/initial blocks
in the design.

However, VHDL does not allow the declaration of
variables at the "architecture" level.
So variables are local to a "process" statement.

A possible solution to this problem is to convert
regs declared at the global level into signals
and "local" regs to "variables". But this solution
is not without problems.

Consider a sequential assignment to a "global reg"
inside an always block. This becomes a signal assignment
statement in VHDL.

=======================           =======================
module X(....);                   entity X(....)
reg A;                            end;

                          ====>   architecture SYN of X

  A = 1'0;                        begin
                                     process (clk)
                                     begin
                                       if (clk'event and clk=1)
                                         begin
                                           A <= '0';
                                           wait for 0 ns;
                                         end
                                       endif
                                     end process;
                                  end;
==========================        ==============================

Please note the "wait for 0 ns" statement which
follows the signal assignment statement in VHDL.

This is required so that the value '0' is assigned to
signal 'A' immediately, i.e. before the next sequential
statement, if any, in the process is executed (there are
none, in this example).

But this methodology could pose problems because
the "wait for 0 ns" statement introduced may cause
some event in another process statement to be processed
before returning to the current process statement which
could, in general, cause some problems.

Any solution to this problem is welcome.

Thanks for your time.

Regards,
Nagendra

Sent via Deja.com http://www.*-*-*.com/
Before you buy.



Fri, 12 Apr 2002 03:00:00 GMT  
 Verilog-VHDL conversion - simulation semantics
Verilog regs and wires are both signals in VHDL.
Quote:

> Hi,

> I'm trying to convert an existing Verilog design
> to a VHDL design.

> The methodology I'm following is as follows.
> All "regs" in Verilog become "variables" in VHDL,
> and all "wires" become "signals".

> However, I've a problem here. Verilog allows
> declaration of "regs" at the "module" level,
> that is outside an "always" block. These "regs"
> can be used in all the always/initial blocks
> in the design.

> However, VHDL does not allow the declaration of
> variables at the "architecture" level.
> So variables are local to a "process" statement.

> A possible solution to this problem is to convert
> regs declared at the global level into signals
> and "local" regs to "variables". But this solution
> is not without problems.

> Consider a sequential assignment to a "global reg"
> inside an always block. This becomes a signal assignment
> statement in VHDL.

> =======================           =======================
> module X(....);                   entity X(....)
> reg A;                            end;

>                           ====>   architecture SYN of X

>   A = 1'0;                        begin
>                                      process (clk)
>                                      begin
>                                        if (clk'event and clk=1)
>                                          begin
>                                            A <= '0';
>                                            wait for 0 ns;
>                                          end
>                                        endif
>                                      end process;
>                                   end;
> ==========================        ==============================

> Please note the "wait for 0 ns" statement which
> follows the signal assignment statement in VHDL.

> This is required so that the value '0' is assigned to
> signal 'A' immediately, i.e. before the next sequential
> statement, if any, in the process is executed (there are
> none, in this example).

> But this methodology could pose problems because
> the "wait for 0 ns" statement introduced may cause
> some event in another process statement to be processed
> before returning to the current process statement which
> could, in general, cause some problems.

> Any solution to this problem is welcome.

> Thanks for your time.

> Regards,
> Nagendra

> Sent via Deja.com http://www.deja.com/
> Before you buy.



Fri, 12 Apr 2002 03:00:00 GMT  
 Verilog-VHDL conversion - simulation semantics

Quote:

> Verilog regs and wires are both signals in VHDL.

Not so. A Verilog reg can have semantics similar to
VHDL variables, shared variables, signals, and all
of these at the same time - depending on how it
is used.

Jan

--
Jan Decaluwe           Easics              
Design Manager         System-on-Chip design services  
+32-16-395 600         Interleuvenlaan 86, B-3001 Leuven, Belgium



Fri, 12 Apr 2002 03:00:00 GMT  
 Verilog-VHDL conversion - simulation semantics

Quote:

> Hi,

> I'm trying to convert an existing Verilog design
> to a VHDL design.
> The methodology I'm following is as follows.
> All "regs" in Verilog become "variables" in VHDL,
> and all "wires" become "signals".

That's too simple.

Quote:
> However, I've a problem here. Verilog allows
> declaration of "regs" at the "module" level,
> that is outside an "always" block. These "regs"
> can be used in all the always/initial blocks
> in the design.

> However, VHDL does not allow the declaration of
> variables at the "architecture" level.

VHDL'93 does, but you have to declare them - quite
appropriately - as "shared" variables.

Quote:
> So variables are local to a "process" statement.

> A possible solution to this problem is to convert
> regs declared at the global level into signals
> and "local" regs to "variables". But this solution
> is not without problems.

The problem is that Verilog regs can serve as (shared)
variables and VHDL-like signals *depending on how
they are used*. You can use both variable assignment
and "signal" assignment ('<=') on them. The strange
Verilog terminology for this is blocking vs. non-blocking
assignment.

So you will have to inspect how a reg is used, and then
declare it as a shared variable or a signal in VHDL. If
you can determine that the reg is only driven from
a single always block, you can declare it locally in the
equivalent process instead.

In Verilog, I am sure, you can even mix blocking and
non-blocking assignments. In such a case, you are in
trouble. Well, not only you, but also the poor
maintainer of the original code.

Regards, Jan

--
Jan Decaluwe           Easics              
Design Manager         System-on-Chip design services  
+32-16-395 600         Interleuvenlaan 86, B-3001 Leuven, Belgium



Fri, 12 Apr 2002 03:00:00 GMT  
 Verilog-VHDL conversion - simulation semantics

Quote:

> If you can determine that the reg is only driven from
> a single always block, you can declare it locally in the
> equivalent process instead.

.. but only if the reg is being used as a variable, of course.

--
Jan Decaluwe           Easics              
Design Manager         System-on-Chip design services  
+32-16-395 600         Interleuvenlaan 86, B-3001 Leuven, Belgium



Fri, 12 Apr 2002 03:00:00 GMT  
 Verilog-VHDL conversion - simulation semantics
Hi,

The solution will somewhat depend on why you are using a blocking
assign in the Verilog to begin with. If you want to use the value
of updated value of A immediately, then here's one solution:

// Source Verilog
module test(clk);

   input clk;
   reg A, B;


      A = 1'b0;
      B <= A;
   end

endmodule

-- Translated code
ENTITY test IS
   PORT (clk                     : IN std_logic);  
END test;

ARCHITECTURE translated OF test IS
   SIGNAL A                        :  std_logic;  
   SIGNAL B                        :  std_logic;  
BEGIN
   PROCESS (clk)
      VARIABLE A_xhdl1  : std_logic;
   BEGIN
      IF (clk'EVENT AND clk = '1') THEN
         A_xhdl1 := '0';    
         B <= A_xhdl1;    
      END IF;
      A <= A_xhdl1;
   END PROCESS;
END translated;

If, on the otherhand, you want to use the updated value of A in
another concurrent block, either use the WAIT trick or consider
using a non-blocking assignment in the Verilog.

Basically, you need to look at why a blocking assignment is used
then tailor your translation to mimic the needed functionality.

To help with basic translation issues, you can download the demo
version of X-Tek's X-HDL translator and try out cases like this.
The URL is: www.x-tekcorp.com

Hope this helps.

Tom

Quote:
>>>>>>>>>>>>>>>>>> Original Message <<<<<<<<<<<<<<<<<<


regarding Verilog-VHDL conversion - simulation semantics:
Quote:
> Hi,
> I'm trying to convert an existing Verilog design
> to a VHDL design.
> The methodology I'm following is as follows.
> All "regs" in Verilog become "variables" in VHDL,
> and all "wires" become "signals".
> However, I've a problem here. Verilog allows
> declaration of "regs" at the "module" level,
> that is outside an "always" block. These "regs"
> can be used in all the always/initial blocks
> in the design.
> However, VHDL does not allow the declaration of
> variables at the "architecture" level.
> So variables are local to a "process" statement.
> A possible solution to this problem is to convert
> regs declared at the global level into signals
> and "local" regs to "variables". But this solution
> is not without problems.
> Consider a sequential assignment to a "global reg"
> inside an always block. This becomes a signal assignment
> statement in VHDL.
> =======================           =======================
> module X(....);                   entity X(....)
> reg A;                            end;
>                           ====>   architecture SYN of X

>   A = 1'0;                        begin
>                                      process (clk)
>                                      begin
>                                        if (clk'event and clk=1)
>                                          begin
>                                            A <= '0';
>                                            wait for 0 ns;
>                                          end
>                                        endif
>                                      end process;
>                                   end;
> ==========================        ==============================
> Please note the "wait for 0 ns" statement which
> follows the signal assignment statement in VHDL.
> This is required so that the value '0' is assigned to
> signal 'A' immediately, i.e. before the next sequential
> statement, if any, in the process is executed (there are
> none, in this example).
> But this methodology could pose problems because
> the "wait for 0 ns" statement introduced may cause
> some event in another process statement to be processed
> before returning to the current process statement which
> could, in general, cause some problems.
> Any solution to this problem is welcome.
> Thanks for your time.
> Regards,
> Nagendra
> Sent via Deja.com http://www.deja.com/
> Before you buy.



Fri, 12 Apr 2002 03:00:00 GMT  
 Verilog-VHDL conversion - simulation semantics
Have you considered the use of a conversion program? Awhile back I played
with something called X-HDL and found the results to be very good.

Cheers,
Jamie


Quote:
> Hi,

> I'm trying to convert an existing Verilog design
> to a VHDL design.



Tue, 23 Apr 2002 03:00:00 GMT  
 Verilog-VHDL conversion - simulation semantics

Quote:

> > However, VHDL does not allow the declaration of
> > variables at the "architecture" level.

> VHDL'93 does, but you have to declare them - quite
> appropriately - as "shared" variables.

Sorry, I forgot to mention that I'm working
with a VHDL simulator which supports only VHDL'87.

Quote:
> The problem is that Verilog regs can serve as (shared)
> variables and VHDL-like signals *depending on how
> they are used*. You can use both variable assignment
> and "signal" assignment ('<=') on them. The strange
> Verilog terminology for this is blocking vs. non-blocking
> assignment.

> So you will have to inspect how a reg is used, and then
> declare it as a shared variable or a signal in VHDL. If
> you can determine that the reg is only driven from
> a single always block, you can declare it locally in the
> equivalent process instead.

> In Verilog, I am sure, you can even mix blocking and
> non-blocking assignments. In such a case, you are in
> trouble. Well, not only you, but also the poor
> maintainer of the original code.

Yes, I realize that the conversion becomes
all the more complicated if the global register
is used on the LHS of both blocking and non-blocking
assignments.

Regards,
Nagendra

Sent via Deja.com http://www.deja.com/
Before you buy.



Sat, 27 Apr 2002 03:00:00 GMT  
 Verilog-VHDL conversion - simulation semantics


Quote:
> Have you considered the use of a conversion program? Awhile back I
played
> with something called X-HDL and found the results to be very good.

> Cheers,
> Jamie

Hi,

I realize that Verilog-VHDL conversion is not
an easy problem to solve. Tools which are available
(I'm not referring to any particular tool)
either do not support all Verilog features or
generate VHDL which may not be semantically
equivalent to the original Verilog code or worse
still, they end up generating VHDL code which does
not even compile.

To be fair to them, we have to accept that
Verilog-VHDL conversion which does not require any
user intervention is impossible. So the utility
of such conversion tools is limited.

Regards,
Nagendra

Sent via Deja.com http://www.deja.com/
Before you buy.



Sat, 27 Apr 2002 03:00:00 GMT  
 
 [ 9 post ] 

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