leonardo synthesize tool (exemplar) 
Author Message
 leonardo synthesize tool (exemplar)

I tried to synthesize my VHDL code (high level behaviour description) by
Leonardo synthesize tool, and the D Flip-Flop (DFF_1) cell involved uses up
to 300 gate counts!! That shouldn't happen.  Therefore the reported area (in
terms of  total gate counts) is incredibly large.
does anyone know where I might set the settings wrong or any other possible
reasons?


Sun, 09 Jun 2002 03:00:00 GMT  
 leonardo synthesize tool (exemplar)

Quote:

>I tried to synthesize my VHDL code (high level behaviour description) by
>Leonardo synthesize tool, and the D Flip-Flop (DFF_1) cell involved uses up
>to 300 gate counts!! That shouldn't happen.  Therefore the reported area
(in
>terms of  total gate counts) is incredibly large.
>does anyone know where I might set the settings wrong or any other possible
>reasons?

Perhaps your description of the D flipflop wasn't what the synthesizer
requires?  Generally, your flipflop process's sensitivity list should only
have the clock and perhaps an async reset:

flop : process (clock, reset) is
begin
    if reset = '1' then
        q <= '0';
    elsif rising_edge(clock) then
        q <= d;
    end if;
end process flop;

Anything else might confuse the synthesizer and instead of using a flop, it
tries to build your desired circuit out of gates.

post your code.

-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

The secret of Slurm is on a need-to-know basis.



Sun, 09 Jun 2002 03:00:00 GMT  
 
 [ 2 post ] 

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