SNUG Europe 1994 Final Schedule 
Author Message
 SNUG Europe 1994 Final Schedule

                    SNUG Europe 1994 Agenda & Registration

Third Meeting, September 20-21, Grenoble, France

The Third Annual Synopsys European Users Group Conference (SNUG Europe)
will take place this year in Grenoble on Tuesday and Wednesday, September
20/21 during EURO-DAC with EURO-VHDL 1994. SNUG Europe will be held at
                                Hotel Prisident
                                rue Giniral Mangin
                                31000 Grenoble
                                tel: +33-76-56-26-56

Conference Agenda Overview

The conference will be held in two parts:- on Tuesday afternoon there will
be presentations from Synopsys users and semiconductor vendor partners; on
Wednesday morning three tutorials are to be given by Synopsys product
specialists. This agenda is based on the best available information
currently available.

Tuesday 20th - User Conference

11.30-12.30     Registration & Buffet Lunch

12.30-13.30     Welcome and Keynote Address
                Synopsys Executive Q&A

13.45-15.45     Session 1
         1A     User Presentations
                Design Productivity
         1B     User Presentations
                Tool Productivity
         1C     Semiconductor Partner Design Flow & Support

16.00-18.00     Session 2
         2A     User Presentations
                Design Productivity
         2B     User Presentations
                Tool Productivity
         2C     Semiconductor Partner Design Flow & Support

19.15-Late      SNUG Europe Party

Wednesday 21st - Tutorials

8.30-9.00       Tutorial Registration

    Tutorial A  VHDL Coding Tricks and Techniques
    Tutorial B  Advanced HDL Methodology
    Tutorial C  "Pins-Out" Design Verification

12:00-13:00     HP-Sponsored Buffet Lunch

Agenda Details -Tuesday 20th September

Design Productivity
Session 1A

This session will feature four presentations on "Pins Out" simulation. In
other words the papers will deal with issues of simulating ASICs in their
board context, using simulation to make system design tradeoffs and
simulating multi-chip systems.

Thomas Albrecht, Siemens Wien, "VHDL-Based Processor Board Simulation in a
Top-Down-Design Environment - the Board: Heart of the Enhanced CCS7E Unit
of the EWSD-System developed by Siemens AG, Public Communication Networks

E. Hansson, W. Buchhuber, S. Eckart, P. Kindsmuller, P. Kuhn, Technical
University Munich, "System Level Verification Environment for an ATM Chip"

Claus Schneider, Siemens-Nixdorf Informationssysteme, "Optimizing DMA
System Performance using Behavi{*filter*}VHDL Simulation"

Lynn Watson, Hewlett Packard , "System Simulation as an ASIC Development

Session 2A

This session will  start with a report on experiences of using COSSAP for
system level design then is followed by three presentations on ASIC design

Tero Kuusinen, Nokia Mobile Phones, "COSSAP, a new tool in our design flow"

F. Calvo, P. Mateos, J. Crespo, J. Solana, A. Altadill, R. Caravantes,
Telefonica I+D, "User Experiences with Synopsys for the Development of Two
Complex High-speed ASICs with LSI Logic"

Neil Hand, Ellemtel Telecommunication Systems Laboratories, "Designing with
Semic-custom Embedded Arrays - Some Design Experiences"

Samir Sanghani, Sun Microsystems Inc., "Integrating Synopsys in a
Structured-Custom Design Flow"

Tool Productivity
Session 1B

DesignWare and TestCompiler are the first topics in this session followed
by two contributions on using synthesis.

Jerry Machado, Altera Corporation, "Synopsys DesignWare enhances Altera's
Programmable Logic Interface"

Sven-Ake Andersson,  Ellemtel, "Mongoose Test Generation Environment"

Patrick Vandebroek & Stefaan Note, Philips ITCL, "An HDL Synthesis Script
for Datapath Dominated, Hierarchical Digital Signal Processing ASIC

Manfred Selz, Universitdt Erlangen-N|rnberg, "Strategies for Timing
Optimization with Design Compiler", Universitaet Erlangen-N|rnberg

Session 2B

The last paper on synthesis is followed by DSP-related topics using COSSAP

Aurelio Monti, Alcatel Telettra, "Automation of the Synthesis Process -
Alcatel Telettra Experience"

Terrence Yim, Nokia Mobile Phones, "Building COSSAP Models using
Object-oriented Languages"

P. Taaghol, R. Tarafazolli & B.G. Evans, University of Surrey, "Power
Control in CDMA Personal Communication Systems (PCNs)"

Marylin Arndt, CNET, "Design of a videochip: a top down methodology using
COSSAP and synthesis tools"

Session 3B

This session contains a pre-view of the new Behavi{*filter*}Compiler product.

Kris Croes, IMEC, "Early Experiences with Synopsys Behavi{*filter*}Compiler"

Semiconductor Vendor Partner Session
Session 1C

This session includes presentations on design flows from invited
semiconductor vendors

Udo Porsch, Fujitsu Mikroelektronik GmbH, "Synopsys Design Flow integrated
in Fame5"

Carol Fields, Xilinx Corporation, "Advantages of using XSI 3.1"

Robert Cottrell, LSI Logic,  "Predictable submicron design with Synopsys
and LSI Logic"

Doug Amos, Altera Europe, "FPGA or Design Compiler gets complete top-down
support for Altera CPLDs"

Session 2C

This session includes presentations on design flows from invited
semiconductor vendors

Paul Williams, Texas Instruments, "TI/Synopsys Signoff ASIC Flow, with
embedded memories and ARM7 core"

Andy Biddle, Actel Europe, "Antifuse FPGAs for synthesis friendly results"

Jean-Pierre Schoellkopf, SGS-Thomson, "SGS-Thomson libraries and ASIC
design flow with Synopsys tools"

SNUG Europe Party

This year's SNUG cultural event will take place at the beautiful Chbteau de
Touvet, which is situated 30km outside Grenoble at the foot of the
Chartreuse mountains. The party will start with a reception in the
courtyard followed by a gourmet dinner with fine wines at l'Orangerie. The
evening will conclude late with a jazz band and open bar. This will provide
a relaxing opportunity to meet other Synopsys users and members of the
Synopsys team.

Bus transport will be provided from Hotel Prisident and some other hotels
to Le Touvet at 19:10. Return buses will run at 23:00 and 00:30.

Agenda Details -Wednesday 21st September


VHDL Coding Tricks and Techniques

This tutorial will present a wide range of tricks and techniques that will
improve the participants' overall VHDL productivity. Caveats based on
real-world coding scenarios will be explored and innovative solutions to
these problems will be provided in full detail. Topics will be presented in
the following areas: efficient VHDL models, unexpected analyze errors,
unexpected simulation results and modeling recommendations.

Pins Out Simulation

 As the complexity of ASICs increases, validation of functionality and the
trading-off of design parameters for the ASIC becomes more difficult. First
time right ASIC design depends on correctinteractions between the ASIC and
surrounding subsystems. Thus it is important to simulate the ASIC in its
system context; in other words to simulate "Pins Out".

Successful Pins Out simulation depends on effective modeling of the ASIC's
environment. This can be achieved through a combination of VHDL and
standard part models. The VHDL model for the ASIC and its environment can
additionally be used to examine design tradeoffs for the ASIC and for its
environment  at a high level. This tutorial introduces the Pins Out
methodology and shows some of its benefits. It is also shown how hardware
and software models can be linked to the VHDL System Simulator for Pins Out
verification. Finally, VHDL examples are used to show how Pins Out
verification fits into the complete high level design process.

High Level Design Methodology

This tutorial will explore the entire high level design methodology. The
content is geared toward Synopsys VHDL simulation and synthesis users. This
tutorial will explore every aspect of high level design including: System
level simulation, high level design considerations, coding styles,
simulation techniques, module synthesis and integration, and structural
verification.  The tutorial will identify a recommended flow through the
entire tool set.

HP Sponsored Buffet Lunch

Following the tutorials, a buffet lunch will be kindly provided by Hewlett
Packard, supplier of leading edge workstations.

Advance Registration

Please complete the Advance Registration form below and fax it to Corinna
Voss at HBI (note that fees are only payable on-site in Grenoble - see

                                HBI Helga Bailey International GmbH
                                Stefan-George-Ring 2
                                D-81929 Munchen
                                tel: +49-89-93-50-81
                                fax: +49-89-930-24-45

If you wish to register by e-mail, please send the requested information to

Registration fees are ONLY payable on-site in Grenoble.

The fee will be payable EITHER as cash or EuroCheque for FF600.-


by American Express, Master Card or VISA credit card payment for US $120.-.


SNUG Europe 1994 Advance Registration Form

Personal Details (Please duplicate this form for multiple attendees):

Name:           _________________________________
Title:          _________________________________
Company:        _________________________________
Address:        _________________________________

Phone:  ___________________             Fax:    ______________________
e-mail address: ______________

Tutorial Participation

-  VHDL Coding Tricks and Techniques
-  Pins Out Simulation
-  High Level Design Methodology
-  I will not be attending a tutorial on Wednesday morning

Hotel in Grenoble (if known):

 Trapped trying to figure out a Synopsys bug?  Want to hear how 3074 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!

     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."

Tue, 04 Mar 1997 17:07:16 GMT  
 [ 1 post ] 

 Relevant Pages 

1. SNUG Europe 1994 Final Schedule

2. Revised Schedule for 1994 Tcl/Tk Workshop

3. Tcl/Tk 1994 Workshop Schedule

4. TOOLS Europe '94 March 7-10, 1994, Versailles-France (long)

5. TOOLS Europe '94 March 7-10, 1994, Versailles-France (long)

6. Final CFP: 1994 Ada-Belgium Seminar

7. Final Program: 1994 IEEE-CS Computer Languages Conference

8. Final Program: 1994 IEEE-CS Computer Languages Conference

9. REXXLIST Digest - 23 Sep 1994 to 24 Sep 1994

10. SNUG Europe Advanced Notice & CFP


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