VHDL models of Viewlogic primatives 
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 VHDL models of Viewlogic primatives

I am looking for a set of VHDL models which have the same functionality as
the viewlogic viewsim primatives.  I am using export1076 to translate an
old design into VHDL for use in a vhdl testbench.  The export1076 works
great and generates a vhdl netlist showing the interconnection of all the
instantiations.  Unfortunatly this process still requires some low level
vhdl functional models of the primative cells.  We have tried calling
viewlogic and they say they do not have these vhdl primatives(It seems
like an obvious addition to there export 1076 tool), but they said to go
write our own. Does anyone have a set already done?


Sun, 11 Apr 1999 03:00:00 GMT  
 [ 1 post ] 

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