double clocked register? 
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 double clocked register?

Does it possable in VHDL to make the register, clocked with CLK1, if you
write and with CLK2, if you read (and  with CLK3 for shift ).

  fliser6.vcf
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Sun, 24 Mar 2002 03:00:00 GMT  
 double clocked register?

Quote:

> Does it possable in VHDL to make the register, clocked with CLK1, if
> you write and with CLK2, if you read (and  with CLK3 for shift ).

Ilia,

it's possible in VHDL, however I don't see a way to get it synthesized
to real hardware (which is the point of using VHDL, right? At least when
you are talking about a register.).

Besides, I don't understand what you mean with CLK2 for reading -
normally, a register doesn't need a clock to be read, its value is
constantly available at the output. Register banks or memories are
another matter.

Greetings,

Georg

--
All opinions expressed are mine, not my employers'.

Georg Diebel, Inst. for Integrated Circuits, Technical University of
Munich

  Phone: 0049-89-289-28578
  Homepage: http://www.lis.e-technik.tu-muenchen.de/people/gd.html



Sun, 24 Mar 2002 03:00:00 GMT  
 double clocked register?

Quote:

> Does it possable in VHDL to make the register, clocked with CLK1, if you
> write and with CLK2, if you read (and  with CLK3 for shift ).

>   ------------------------------------------------------------------------


>   Robert Bosch GmbH, FV/FLI

Sure, as long as you aren't trying to synthesize it. (I am assuming you
mean a flip-flop type of register with 3 clock signals)

To do it with priority:

  process...
  begin
    if (rising_edge(CLK1)) then
      ...
    elsif (rising_edge(CLK2)) then
      ...
    elsif (rising_edge(CLK3)) then
      ...
    end if;
  end process;

The other alternative if you want something to synthesize is come up
with some sort of clock gating circuit that directs the correct clock to
the register depending upon the operation to be performed.

--
Brian C. Boorman
Harris RF Communications
Rochester, NY 14610

<Remove the XYZ. for valid address>



Sun, 24 Mar 2002 03:00:00 GMT  
 
 [ 3 post ] 

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