Making the Synopsys VSS faster 
Author Message
 Making the Synopsys VSS faster

Hi,

I dont even know if this is correct.  I heard that there is something in the Synopsys
VSS which makes simulation faster. Is there any tool by Synopsys which can do that?
Does any one out there know what it is or whether it is incorrect.

Thanks

---

Hrishikesh  S.                                  Grad. Student
                                                Computer Engineering,


Tel(o): (703)-231-4202                          VA 24060,



Sat, 01 Feb 1997 03:04:26 GMT  
 Making the Synopsys VSS faster

Quote:
(Hrishikesh S.) writes:

Synopsys has both interpreted and compiled modes. Compiled is much faster.
Use the -c option when you run vhdlan.


Sat, 01 Feb 1997 11:16:07 GMT  
 Making the Synopsys VSS faster

Quote:
(Hrishikesh S.) writes:


Synopsys has both interpreted and compiled modes. Compiled is much faster.
Use the -c option when you run vhdlan.

------------------------------------------------------------------------------------
Are you sure, that compiled Simulation with synopsys vss (vhdldbx) is _much_ faster?

I increased the time from starting vhdldbx to the end of simulation just by about
30 percent. I expected to speed it up by a factor of 2 ... 5 or even 10.

I could speed simulation by another factor of 2 by clicking the wave window to an icon
during simulation runtime.

Are there more ways to speed up synopsys simulation?

Dieter Peer



Sat, 08 Feb 1997 21:14:44 GMT  
 Making the Synopsys VSS faster
Hi all,

I am having a problem in trying to map an INOUT port as the actual
for a formal IN port.

The setup is :

ti_in : std_ulogic_vector(3 downto 0);
ti_out_t : std_logic_vector(3 downto 0);

I want to do the following:

architecture ...

test : dummy port map (
        ti_in => ti_out_t);
end arch;

Obviously, I cannot do this directly, because the types are different.
Creating a signal of type Std_ulogic_vector, and tried a signal
assignment did not work either. Do I have to make all the involved
types to be Std_logic_vector? Is there another way of doing this?

P.S - I have seen this kind of question before, but never saved the
replies! Apologies to those who get irritated by seeing this question
so many times.

Thanks,

--
*       Sashi Obilisetty                        *
*       Alternative System Concepts, Inc.       *
*       PO Box 128 Windham NH 03087             *
*       tel (603) 437-2234 fax (603) 437-ASC2   *



Sun, 09 Feb 1997 00:44:58 GMT  
 Making the Synopsys VSS faster

Quote:
>Hi all,

>I am having a problem in trying to map an INOUT port as the actual
>for a formal IN port.

>The setup is :

>ti_in : std_ulogic_vector(3 downto 0);
>ti_out_t : std_logic_vector(3 downto 0);

>I want to do the following:

>architecture ...

>test : dummy port map (
>    ti_in => ti_out_t);
>end arch;

>Obviously, I cannot do this directly, because the types are different.
>Creating a signal of type Std_ulogic_vector, and tried a signal
>assignment did not work either. Do I have to make all the involved
>types to be Std_logic_vector? Is there another way of doing this?

Not taking the time to delve deeply, but there is a conversion function
in std_logic_1164 called To_StdLogicVector with an input std_ulogic_vector
and another called  To_StdULogicVector with an input std_logic_vector.

I would think you could use these perhaps like:

- Show quoted text -

Quote:
>test : dummy port map (
>    ti_in => To_StdULogicVector(ti_out_t));
>end arch;



Sun, 09 Feb 1997 06:09:00 GMT  
 Making the Synopsys VSS faster

Quote:

>Hi all,
>I am having a problem in trying to map an INOUT port as the actual
>for a formal IN port.
>The setup is :
>ti_in : std_ulogic_vector(3 downto 0);
>ti_out_t : std_logic_vector(3 downto 0);
>I want to do the following:
>architecture ...
>test : dummy port map (
>    ti_in => ti_out_t);
>end arch;
>Obviously, I cannot do this directly, because the types are different.
>Creating a signal of type Std_ulogic_vector, and tried a signal
>assignment did not work either. Do I have to make all the involved
>types to be Std_logic_vector? Is there another way of doing this?
>P.S - I have seen this kind of question before, but never saved the
>replies! Apologies to those who get irritated by seeing this question
>so many times.
>Thanks,
>--
>*   Sashi Obilisetty                        *
>*   Alternative System Concepts, Inc.       *
>*   PO Box 128 Windham NH 03087             *
>*   tel (603) 437-2234 fax (603) 437-ASC2   *

To map ports of different types you could use a type conversion fuction.
In this case there exists a type conversion function in the Std_logic_1164 package.

test : dummy port map (
          ti_in => To_StdULogicVector(ti_out_t));

Hope this helps,

Guido
--
Guido Schumacher
Universitaet Oldenburg



Sun, 09 Feb 1997 15:00:53 GMT  
 Making the Synopsys VSS faster

: >I am having a problem in trying to map an INOUT port as the actual
: >for a formal IN port.
: >
: >The setup is :
: >
: >ti_in : std_ulogic_vector(3 downto 0);
: >ti_out_t : std_logic_vector(3 downto 0);
: >
: >I want to do the following:
: >
: >architecture ...
: >
: >test : dummy port map (
: >  ti_in => ti_out_t);
: >end arch;
: >
: >Obviously, I cannot do this directly, because the types are different.
: >Creating a signal of type Std_ulogic_vector, and tried a signal
: >assignment did not work either. Do I have to make all the involved
: >types to be Std_logic_vector? Is there another way of doing this?

: Not taking the time to delve deeply, but there is a conversion function
: in std_logic_1164 called To_StdLogicVector with an input std_ulogic_vector
: and another called  To_StdULogicVector with an input std_logic_vector.

: I would think you could use these perhaps like:

: >test : dummy port map (
: >  ti_in => To_StdULogicVector(ti_out_t));
: >end arch;

Unfortunately, there's one small problem (said in a squeaky, gravelly voice).
Conversion functions used in port maps must be constrained....  If you
write a constrained version of To_StdULogicVector, that should work.

--Paul

--

Menchini & Associates|                           |prove their worth by
2 Davis Dr./POB 13036|    voice: 919-990-9506    |hitting back."
RTP, NC  27709-3036  |    fax:   919-990-9507    |         -- Piet Hein



Mon, 10 Feb 1997 06:09:48 GMT  
 Making the Synopsys VSS faster

Quote:
>Hi all,

>I am having a problem in trying to map an INOUT port as the actual
>for a formal IN port.

>The setup is :

>ti_in : std_ulogic_vector(3 downto 0);
>ti_out_t : std_logic_vector(3 downto 0);

>I want to do the following:

>architecture ...

>test : dummy port map (
>    ti_in => ti_out_t);
>end arch;

>Obviously, I cannot do this directly, because the types are different.
>Creating a signal of type Std_ulogic_vector, and tried a signal
>assignment did not work either. Do I have to make all the involved
>types to be Std_logic_vector? Is there another way of doing this?

>P.S - I have seen this kind of question before, but never saved the
>replies! Apologies to those who get irritated by seeing this question
>so many times.

>Thanks,

>--
>*   Sashi Obilisetty                        *
>*   Alternative System Concepts, Inc.       *
>*   PO Box 128 Windham NH 03087             *
>*   tel (603) 437-2234 fax (603) 437-ASC2   *

Type conversion is required.  VHDL87 will require a signal assignment
statement as shown below.  VHDL92 allows defining the type conversion
as part of the port mapping.

ti_out_u:  std_ulogic_vector(3 downto 0);

  ti_out_t <= std_logic_vector(ti_out_u);

test : dummy port map (
        ti_in => ti_out_u);

Good Luck!

Charles F. Shelor

SHELOR ENGINEERING              VHDL Training, Consulting, and models
3308 Hollow Creek Rd

(817) 467-9367



Sun, 09 Feb 1997 05:39:55 GMT  
 
 [ 9 post ] 

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