VHDL textio 
Author Message
 VHDL textio

Hi,

I'm a final year project and try to program an adaptive noise
canceller.  For this my simulation should be able to read some number
from an ASCII file.
To learn how to handle the textio package i wrote a little trial
program to see how it works.  And following problem occurse.  I try to
read from the
"rein.txt" file and want to write into the "raus.txt" file.  In my
input file "rein.txt", there is in each line one decimal number (1 2 3
4 5 6 ...).  After the simulation there should be same numbers in the
output file "raus.txt".  What now happens is, that all values are
shifted of 1 waitcycle (50ns) and the first value is the last number
from the buffer. So maybe there is one who know the solution...

I would be grateful for any help you can give me

Markus
-----------------------------------------------------------------
entity probe is  
end probe;
architecture GABI of probe is
signal x1, y1: std_logic_vector(7 downto 0);
component reinraus -- y1 <= x1
        port    (x1: in std_logic_vector(7 downto 0);
                 y1: out std_logic_vector(7 downto 0));
end component;
begin
A1: reinraus port map(x1, y1);
P1: PROCESS  
        variable textline: line;
        variable i, o: integer;
        file rein : text open read_mode is "rein.txt";
        file raus : text open write_mode is "raus.txt";
        BEGIN
                IF endfile(rein)=false THEN LOOP
                readline(rein, textline);
                read(textline,i);
                x1 <= conv_std_logic_vector(i,8);
                o := conv_integer(y1);
                write(textline,o);
                writeline(raus,textline);
                WAIT for 50 ns;
                END LOOP;
                END IF;
END PROCESS;
END GABI;
------------------------------------------------------------------



Tue, 31 Aug 2004 20:49:47 GMT  
 VHDL textio
put your
file rein : text open read_mode is "rein.txt";
file raus : text open write_mode is "raus.txt";

before the first begin... NOT in a process,
(ie just after the signals are declared)

else your going to be opening the file again every loop.

--
Benjamin Todd
European Organisation for Nuclear Research
SL SPS/LHC -- Control -- Timing Division
CERN, Geneva, Switzerland,  CH-1211
Building 864 Room 1 - A24
http://benjamintodd.com


Quote:
> Hi,

> I'm a final year project and try to program an adaptive noise
> canceller.  For this my simulation should be able to read some number
> from an ASCII file.
> To learn how to handle the textio package i wrote a little trial
> program to see how it works.  And following problem occurse.  I try to
> read from the
> "rein.txt" file and want to write into the "raus.txt" file.  In my
> input file "rein.txt", there is in each line one decimal number (1 2 3
> 4 5 6 ...).  After the simulation there should be same numbers in the
> output file "raus.txt".  What now happens is, that all values are
> shifted of 1 waitcycle (50ns) and the first value is the last number
> from the buffer. So maybe there is one who know the solution...

> I would be grateful for any help you can give me

> Markus
> -----------------------------------------------------------------
> entity probe is
> end probe;
> architecture GABI of probe is
> signal x1, y1: std_logic_vector(7 downto 0);
> component reinraus -- y1 <= x1
> port (x1: in std_logic_vector(7 downto 0);
>   y1: out std_logic_vector(7 downto 0));
> end component;
> begin
> A1: reinraus port map(x1, y1);
> P1: PROCESS
> variable textline: line;
> variable i, o: integer;
> file rein : text open read_mode is "rein.txt";
> file raus : text open write_mode is "raus.txt";
> BEGIN
> IF endfile(rein)=false THEN LOOP
> readline(rein, textline);
> read(textline,i);
> x1 <= conv_std_logic_vector(i,8);
> o := conv_integer(y1);
> write(textline,o);
> writeline(raus,textline);
> WAIT for 50 ns;
> END LOOP;
> END IF;
> END PROCESS;
> END GABI;
> ------------------------------------------------------------------



Tue, 31 Aug 2004 21:19:31 GMT  
 VHDL textio
Hi,
    The issue is not within TEXTIO, with Signals/Variables.

You say:

Quote:
> read(textline,i);
> x1 <= conv_std_logic_vector(i,8);

  This will "schedule" a transaction on x1 signal (which will essentially
get its new value (read from file) ONLY at the end of this delta cycle -
which is the end of process in this case.

So your DUT (reinraus) sees "x1"'s new value  after the process executes the
following lines:

Quote:
> o := conv_integer(y1);
> write(textline,o);
> writeline(raus,textline);

By now the old value of "y1" gets written to output file.

So you get that 50 ns shift. To solve try using the wait for 50 ns at

Quote:
> read(textline,i);
> x1 <= conv_std_logic_vector(i,8);

WAIT for 50 ns;

Quote:
> o := conv_integer(y1);
> write(textline,o);
> writeline(raus,textline);

Also try and use numeric_std functions like to_unsgined, to_integer instead
of conv_*.

HTH,
Srinivasan
--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt Ltd. - an Intel company
Bangalore, India

I don't speak for Intel

Quote:
> Hi,

> I'm a final year project and try to program an adaptive noise
> canceller.  For this my simulation should be able to read some number
> from an ASCII file.
> To learn how to handle the textio package i wrote a little trial
> program to see how it works.  And following problem occurse.  I try to
> read from the
> "rein.txt" file and want to write into the "raus.txt" file.  In my
> input file "rein.txt", there is in each line one decimal number (1 2 3
> 4 5 6 ...).  After the simulation there should be same numbers in the
> output file "raus.txt".  What now happens is, that all values are
> shifted of 1 waitcycle (50ns) and the first value is the last number
> from the buffer. So maybe there is one who know the solution...

> I would be grateful for any help you can give me

> Markus
> -----------------------------------------------------------------
> entity probe is
> end probe;
> architecture GABI of probe is
> signal x1, y1: std_logic_vector(7 downto 0);
> component reinraus -- y1 <= x1
> port (x1: in std_logic_vector(7 downto 0);
>   y1: out std_logic_vector(7 downto 0));
> end component;
> begin
> A1: reinraus port map(x1, y1);
> P1: PROCESS
> variable textline: line;
> variable i, o: integer;
> file rein : text open read_mode is "rein.txt";
> file raus : text open write_mode is "raus.txt";
> BEGIN
> IF endfile(rein)=false THEN LOOP
> readline(rein, textline);
> read(textline,i);
> x1 <= conv_std_logic_vector(i,8);
> o := conv_integer(y1);
> write(textline,o);
> writeline(raus,textline);
> WAIT for 50 ns;
> END LOOP;
> END IF;
> END PROCESS;
> END GABI;
> ------------------------------------------------------------------



Tue, 31 Aug 2004 22:04:56 GMT  
 
 [ 3 post ] 

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