Announcement: LevBencher VHDL 0.6 Evaluation 
Author Message
 Announcement: LevBencher VHDL 0.6 Evaluation

***** ANNOUNCEMENT *****

Levetate Design Systems is pleased to announce the availability of

     LevBencher VHDL 0.6,

a demonstration version of our new testbench generation product.
Design and verification engineers interested in evaluating LevBencher
are welcome to download the tool from our website at:

      http://www.*-*-*.com/ .

Instructions for installing the tool and running the demo are available
on site.  LevBencher currently runs under Windows 95 and NT 4.0.

LevBencher VHDL is a testbench generation system under development at
Levetate since 1995.  The tool has its origins in NASA-sponsored research
into formal hardware verification performed at the Boeing Company during
1991-1993.  This work was continued at the University of Washington
leading to the first tool prototype in 1994.  LevBencher's marriage of
formal methods and simulations differentiates it from competing approaches
to testbench generation, and we outline some of its advantages below.

***** TOOL FEATURES *****

LevBencher VHDL automatically generates VHDL testbenches from hardware
specifications written in the VHDL Interface Language (VIL).  VIL is
based on VHDL with extensions to efficiently describe behavior over
intervals of time and over multiple levels of abstraction.  VIL's syntax
has been carefully designed to provide intuitive and compact
specifications of complex behavior.  It supports a wide range of
applications besides testbench generation, including formal verification
and behavi{*filter*}synthesis.

LevBencher-generated testbenches are simple, easy to understand, and
fast to execute.  LevBencher analyzes VIL models to eliminate
much of the replicated code and unresolved behavior that would be present
in a lighter weight translation.  A cycle-based testbench option is
available to further address speed-critical functional verification.
Testbench comments link the generated VHDL back to the VIL source.

VIL specifications define the required behavior of designs and the
assumptions levied on their environments.  A unique aspect of VIL is its
ability to link behavior expressed at different levels of abstraction.
For example, VIL models can describe the required behavior of a design
at the RTL and, at the same time, define required functionality in terms
of higher level transactions or instructions.  VIL achieves this by
supporting the mappings necessary to link the RTL signals to the higher
level signals.  While this capability is necessary for multi-level
verifications in formal verification environments, we believe VIL is the
first language offering this capability to simulation environments.

LevBencher uses VIL's inter-level mappings to produce testbenches
instantiating specification-level components alongside design-level
models.  Multi-level testbenches produced by LevBencher use these
specification components to automatically certify data produced by
the design under test.  Furthermore, specification-level environment
components can be incorporated into tests as well.  These can take
the form of generic models of memory, CPU, or bus transactions reused
from system-level simulations, for example.  Further still,
specification-level testbenches produced by LevBencher can be used to
validate the specification models before they are used in these
multi-level tests.

Finally, LevBencher testbenches provide a wide range of input stimulus
modes to guide the selection of input data and event times.  Constant,
random, and exhaustive selection are available for both data and event
times.  Data values can also be read from input files or driven by
instantiated components.  Event times can be selected to exercise corner
cases as well as simultaneous and near-simultaneous events.

New features will be added based on designer feedback.

Best Regards,

David Fura
Levetate Design Systems, Inc.

Fri, 31 Mar 2000 03:00:00 GMT  
 [ 1 post ] 

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