setup and hold modelling in vhdl 
Author Message
 setup and hold modelling in vhdl



Quote:
> hi,
>  can somebody help me in modeling setup and holdtime of an simple
> D-FF in VHDL.
>  i have written the folowing  code for setup time
> (Data_In=Input data, Thd=Hold time, Tsd=setup time)

>   if(rising_edge(clk)) then
>            assert (Data_In'last_event>=Tsd)
>            report"Setup violation"
>       severity error;
>   end if;

>  can somebody help me in modelling hold time

> thanks

Hi,

One more:

process(DATA_IN)
begin
  assert((CLK'last_event > THD) or (CLK = '0'))
    report "Hold violation"
    severity ERROR;
end process;

Regards,



Mon, 28 Jan 2002 03:00:00 GMT  
 
 [ 1 post ] 

 Relevant Pages 

1. setup and hold modelling in vhdl

2. latch setup & hold

3. need help with $setup / $hold

4. Multiple Clock design, setup & hold time violation

5. what is $setup and $hold time?

6. PLI: Setup and Hold monitoring

7. setup hold time

8. setup & hold for latch

9. help with setup and hold time of d-flip flop

10. $setup and $hold

11. Disabling a $setup/$hold checker on a per-instance basis

12. Multiple Clock design, setup & hold time violation

 

 
Powered by phpBB® Forum Software