Hi Dimitris,
It looks like you are applying the SDF to the wrong level of your testbench.
Make sure you are assigning the SDF to the
UUT in the correct level of your testbench. Note the application uses the
instantiation hierarchy so you would use
/uut.
Check also that you are creating the SDF correctly, open it up in an editor
and check the hierarchy is correct in there, ie /sublevel/sublevel,
again this will be an instantiation hierarchy.
While I suspect it isn't a problem check out that ISE is creating an SDF
which is compatible with Modelsim, Synopsys can generate several
versions, I always dumped out 2.1.
Hope it helps
Andre'
Quote:
> Hello!
> I am using Xilinx's ISE 4.2i for writing VHDL and for simulation,
I
> create a testbench and I use it to open Modelsim. By default, Xilinx's ISE
> creates a "uut" instance of my top module. When I try to simulate my
> testbench with Modelsim, the "Behavi{*filter*}VHDL model" and Post-Translate
VHDL
> model" are working fine. But when I try the "Post-Map VHDL model" or
> "Post-Place and Route VHDL model", modelsim first pops up a warning that
> there is no default binding for my component and then says:
> ERROR: lpm_rf32x8_map.sdf: The design does not have an instance named
> '/UUT'.
> (lpm_rf32x8 is the name of my module)
> If anyone knows something about it, please help! Thank you very much,
in
> advance, for your time!
> Dimitris
ISE 4.2 and Modelsim