Free unbugged lex/yacc based grammar for VHDL 
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 Free unbugged lex/yacc based grammar for VHDL

This is a VHDL lexer and parser that I worked on a couple months ago,
but now that I've returned to work, don't have the time or desire to
fix.  The grammar, taken from "VHDL: Hardware Description and Design"
has numerous shift/reduce and reduce/reduce conflicts that need to be
resolved.  I'm releasing the code, free for anyone's use, in hopes
that someone will finish my work.  If you do get the parser up and
working, I'd appreciate a copy of the repaired lexer or parser.

Regards,

Mark Johnson

begin 664 vhdl.tar.gz
<uuencoded_portion_removed>
"`0!=
`
end



Sat, 15 May 1999 03:00:00 GMT  
 
 [ 1 post ] 

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