state encoding in Synplify??? 
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 state encoding in Synplify???

I use VHDL and Synplify to describe and synthesize my design, respectively.
when i designed a state machine, I used the attribute of syn_encoding to
specify the type of state encoding, such as "gray".The number of states in
my
state machine is 20.But when I looked in the log file after synthesis, I
found
my state encoding had been converted to "one-hot" by Synplify automatically.
Why did it do such? I did not need "one-hot". How could i tell it what I
want
the state encoding to be?

Any suggestions and replies would be very appreciated!

jianjie



Wed, 29 Jan 2003 03:00:00 GMT  
 
 [ 1 post ] 

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