Signal Assignment conflicts, What can I do? 
Author Message
 Signal Assignment conflicts, What can I do?

Hi, Guys,

I am a beginner.

I have serval processes in a architecture.

In each process, RESET='0' leads to reset
some signals mainly used in that process.

when simulating, all assignments in RESET='0'
seem useless.

If I comment out all assignments except those in RESET='0',
then all signals can be initialized.

but each process has following structure:

if RESET='0' then
   XXX <= '0';
   ...
elseif CLK'event and CLK='1' then
      ...
end if;

I wonder, is there any rules to follow when
assigning new values to signals?

THANKS

Butcher.



Sun, 14 Nov 2004 06:54:28 GMT  
 Signal Assignment conflicts, What can I do?

Quote:

> when simulating, all assignments in RESET='0'
> seem useless.

> If I comment out all assignments except those in RESET='0',
> then all signals can be initialized.

http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#drivers

  -- Mike Treseler



Mon, 15 Nov 2004 07:04:53 GMT  
 
 [ 2 post ] 

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