signed/unsigned v.s. integer
Author Message
signed/unsigned v.s. integer

Hi everyone,

I am pretty new to vhdl and trying to guess the differences between
signed/unsigned and integer types.

std_logic_arith as they are not standard. Now, talking about
numeric_std types, what is the difference?. Both support logical and
math operators. So, in the common situation of math-operating two
std_logic_vector, is it really necessary to convert to integer?. For
example, in the most simple case, both

library ieee;
use ieee.numeric_std.all;
....
result<=std_logic_vector(to_unsigned(to_integer(unsigned(data_vector1))
+ to_integer(unsigned(data_vector2)),8));

and

result<=std_logic_vector((unsigned(data_vector1) + unsigned
(data_vector2));

works properly. So, witch is the most correct/efficient approach?

Javier

Sent via Deja.com http://www.*-*-*.com/

Mon, 28 Apr 2003 03:00:00 GMT
signed/unsigned v.s. integer

Quote:

> I have discarded std_logic_signed/std_logic_unsigned and
> std_logic_arith as they are not standard. Now, talking about
> numeric_std types, what is the difference?. Both support logical and
> math operators. So, in the common situation of math-operating two
> std_logic_vector, is it really necessary to convert to integer?. For
> example, in the most simple case, both

> library ieee;
> use ieee.numeric_std.all;
> ....

-------------

--don't forget:
use ieee.std_logic_1164.all;

-------------

Quote:
> result<=std_logic_vector(to_unsigned(to_integer(unsigned(data_vector1))
> + to_integer(unsigned(data_vector2)),8));
> and
> result<=std_logic_vector((unsigned(data_vector1) + unsigned
> (data_vector2));

> work properly.

----pretty cool, isn't it?

Quote:
> So, which is the most correct/efficient approach?

-- I like to declare all logic vectors as unsigned.
-- This would give you:

result <= data_vector1 + data_vector2;

-- you can even do:

result <= data_vector1 + 42;

--    mike.treseler at flukenetworks dot com

Mon, 28 Apr 2003 03:00:00 GMT

 Page 1 of 1 [ 2 post ]

Relevant Pages