Mixed Design Problem (FPGA Express/ACTEL) 
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 Mixed Design Problem (FPGA Express/ACTEL)

Hi everybody,

I am trying to implement with Viewlogics FPGA Express a mixed design
(schematic/VHDL)  in an ACTEL FPGA without success.

What is the right way to implement:
a)
- generate an EDIF netlist from VHDL design with FPGA Express
- invoke EDIF netlist reader to build *.wir file
- build schematic and symbol from *.wir file with ViewGen
- implement symbol (with hidden VHDL design) in topdesign (schematic)
- export EDIF netlist
- invoke ACTEL Designer

b) (do it the XILINX way)
- generate symbol from VHDL design (e.g. VHDL2SYM.exe)
- implement symbol (with hidden VHDL design) in topdesign (schematic)
- invoke fepreproc to build *.edn
- start FPGA Express (New Project with schematic (*.edn) and vhdl (*.vhd)
files)
- export EDIF netlist from optimized chip
-> this works (fine?) for Xilinx designs but for ACTEL designs this EDIF
netlist is empty accept some general things

c) forget mixed design

Way a) seems untypical for me!
What is wrong in b)

Waiting for answers, Ingo.



Sun, 30 Dec 2001 03:00:00 GMT  
 Mixed Design Problem (FPGA Express/ACTEL)
We currently are doing a project in OrCAD that is in schematic form and it
contains a few blocks with VHDL.  What we end up doing is creating a VHDL
netlist from the schematic.  Take that netlist plus the VHDL code for the
few blocks along with the library of components for the Actel FPGA (this is
included with OrCAD) and run them all through Leonardo Spectrum to get your
EDIF.  Then just run that with your pin file through the Actel designer.  I
don't know what schematic package you are using but look to see if you can
make the VHDL netlist and obtain the VHDL  component library.

Hope this helps.


Quote:
> Hi everybody,

> I am trying to implement with Viewlogics FPGA Express a mixed design
> (schematic/VHDL)  in an ACTEL FPGA without success.

> What is the right way to implement:
> a)
> - generate an EDIF netlist from VHDL design with FPGA Express
> - invoke EDIF netlist reader to build *.wir file
> - build schematic and symbol from *.wir file with ViewGen
> - implement symbol (with hidden VHDL design) in topdesign (schematic)
> - export EDIF netlist
> - invoke ACTEL Designer

> b) (do it the XILINX way)
> - generate symbol from VHDL design (e.g. VHDL2SYM.exe)
> - implement symbol (with hidden VHDL design) in topdesign (schematic)
> - invoke fepreproc to build *.edn
> - start FPGA Express (New Project with schematic (*.edn) and vhdl (*.vhd)
> files)
> - export EDIF netlist from optimized chip
> -> this works (fine?) for Xilinx designs but for ACTEL designs this EDIF
> netlist is empty accept some general things

> c) forget mixed design

> Way a) seems untypical for me!
> What is wrong in b)

> Waiting for answers, Ingo.



Mon, 31 Dec 2001 03:00:00 GMT  
 
 [ 2 post ] 

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