Learning VHDL 
Author Message
 Learning VHDL

We have had a minimal exposure to VHDL here and in the
future will be dealing with it more and more.  The goal
is to get to a moderately high level of competence in
our technical support group.  To this end can anyone
reccommend a good tutorial from which we can teach
ourselves?  I would also like to know if there are any
reference works on the market which have been well
received.  Lastly do any of you have knowlege of VHDL
training courses offered?  Any information to assist
us coming up the VHDL learning curve will be greately
appreciated.

                                                    Thanks
                  AAge Gribskov



Sat, 29 Jun 1996 03:41:31 GMT  
 Learning VHDL
Two of the professors here are {*filter*}ia Tech have written a book on structured vhdl
modeling and coding.  I myself have taken their course and bought their book after
it was published in hardback and highly recommend it...

Title:  Structure Logic Design with VHDL
Authors:  James R. Armstrong and F. Gail Gray

Al



Sat, 29 Jun 1996 05:17:35 GMT  
 Learning VHDL
What I believe is one of my better books on the subject of VHDL is
"A GUIDE TO VHDL" by Stanley Mazor and Patricia Langstraat.  It
has the Synopsys name on it, but it is a really good basic book.


Sun, 30 Jun 1996 23:20:26 GMT  
 Learning VHDL

Quote:
>What I believe is one of my better books on the subject of VHDL is
>"A GUIDE TO VHDL" by Stanley Mazor and Patricia Langstraat.  It
>has the Synopsys name on it, but it is a really good basic book.

I agree, it has a good format for learning.  However, I've caught a few
errors.  E.G. Figure 2-15, precedence chart shows "NOT" with logical
operators, but it is actually in miscellaneous and highest precedence.
"ABS", "MOD", and "REM" are also misplaced.  There are a few errors in
punctuation here and there in the sample code and BNF descriptions.


Mon, 01 Jul 1996 03:33:53 GMT  
 Learning VHDL

Quote:

>We have had a minimal exposure to VHDL here and in the
>future will be dealing with it more and more.  The goal
>is to get to a moderately high level of competence in
>our technical support group.  To this end can anyone
>reccommend a good tutorial from which we can teach
>ourselves?  I would also like to know if there are any
>reference works on the market which have been well
>received.  Lastly do any of you have knowlege of VHDL
>training courses offered?  Any information to assist
>us coming up the VHDL learning curve will be greately
>appreciated.

Just as a point of information, Aage, the Rule of Thumb in learning
hardware description languages is that it takes about two weeks of
intensive study to learn enough Verilog to be productive and about
two months to learn VHDL to become productive.  (This is because Verilog
is extremely C-like in look & feel and most EE's get C training somewhere
along the way.  Whereas VHDL is very Ada-like.  (And most EE's have never
even seen Ada much less worked with it.  It's sorta like COBAL on
steriods.  The mindset in this language is very verbose and completely
unlike C in most ways.))

                              - John Cooley
                                the ESNUG guy
                                (and EDA & ASIC Design Consultant, too!)

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 2226 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!


     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."



Tue, 02 Jul 1996 01:25:00 GMT  
 Learning VHDL

Quote:

>Just as a point of information, Aage, the Rule of Thumb in learning
>hardware description languages is that it takes about two weeks of
>intensive study to learn enough Verilog to be productive and about
>two months to learn VHDL to become productive.  

Not in our experience. After a 3 day Synopsys VHDL course, and some
hand-holding, we have found that even people who have never used a HDL
before can write useable synthesizable code in 1-2 weeks. Of course,
synthesizable code only scratches the surface of the language, but it
gets our jobs done.

To do this, we did have to establish coding standards and examples, and
some support software to automatically generate the boilerplate that
VHDL requires (configurations, entity and component declarations etc.)
We also found the VHDL mode for emacs to be very useful.

I'd say that maybe 50% of the VHDL language is excess baggage for normal
hardware design, so most designers don't need to learn it. About 35% of
the other 50% is almost well suited for high level modelling of complex
concurrent systems, with accurate timing. (flame away)

Mark
not speaking for Intel.



Tue, 02 Jul 1996 02:34:04 GMT  
 Learning VHDL

Quote:

>Just as a point of information, Aage, the Rule of Thumb in learning
>hardware description languages is that it takes about two weeks of
>intensive study to learn enough Verilog to be productive and about
>two months to learn VHDL to become productive.  (This is because Verilog
>is extremely C-like in look & feel and most EE's get C training somewhere
>along the way.  Whereas VHDL is very Ada-like.  (And most EE's have never
>even seen Ada much less worked with it.  It's sorta like COBAL on
>steriods.  The mindset in this language is very verbose and completely
>unlike C in most ways.))

At the risk of starting a flame war (in which I shall not participate), I
disagree.  I have personally taught VHDL to several thousand engineers having
a variety of backgrounds, and I've seen the majority of them, when taking a
1 week class immediately prior starting intensive use of VHDL, get productive
in 2-3 weeks.

Of course, some of them "get it" more quickly than that, and some of them
never do.

--Paul
--
Paul Menchini           Menchini & Associates               "Any clod can have the

P.O. Box 13036          voice: 919-990-9506              opinion is an art!"
RTP, NC  27709-3036     fax:   919-990-9507                  -- Charles McCabe



Tue, 02 Jul 1996 04:11:22 GMT  
 Learning VHDL

Quote:


>>Just as a point of information, Aage, the Rule of Thumb in learning
>>hardware description languages is that it takes about two weeks of
>>intensive study to learn enough Verilog to be productive and about
>>two months to learn VHDL to become productive.  

>Not in our experience. After a 3 day Synopsys VHDL course, and some
>hand-holding, we have found that even people who have never used a HDL
>before can write useable synthesizable code in 1-2 weeks. Of course,
>synthesizable code only scratches the surface of the language, but it
>gets our jobs done.

>To do this, we did have to establish coding standards and examples, and
>some support software to automatically generate the boilerplate that
>VHDL requires (configurations, entity and component declarations etc.)
>We also found the VHDL mode for emacs to be very useful.

>I'd say that maybe 50% of the VHDL language is excess baggage for normal
>hardware design, so most designers don't need to learn it. About 35% of
>the other 50% is almost well suited for high level modelling of complex
>concurrent systems, with accurate timing. (flame away)

There's nothing here that warrents flames in my opinion.

What you describe is what a lot of beginning VHDL users do to get up and
running in the language.  (That is, they depend heavily on examples and
they take sort of a "cut and paste" approach to using the language.  I've
even had customers who've asked outright: "Could you just give me an
example to do XYZ and I'll expand it to my application?")

In my opinion and other VHDL users opinion this isn't really knowing the
language but more like parroting the language.  In fact, this was a common
complaint I heard at the last VUIF meeting in California - that lots of
users weren't really learning VHDL but sort of getting by via mimicing
examples they found somewhere.  At times this lack of knowlege in the VHDL
user community got in the way of some discussions because some people would
discuss some intricacy of VHDL only to be followed with another person asking
a fundamental question that clearly demonstrated that the intricacy was
lost on that novice user.

I've also known VHDL users who mimiced for years just getting by.  Stuff
like "I've designed three ASICs using VHDL." yet not knowing what a generic is.

To really get into the mindset of VHDL it takes about two months.  At this
point, the user who's been using it throughout that time can write freestyle
(i.e. no mimicing) what he cares to model whether it be state machines or
testbenches or tectonic plate interactions.  (At the last VUIF one user
explained how he knew a geologist who used VHDL to model plate tectonics.)

                              - John Cooley
                                the ESNUG guy
                                (and EDA & ASIC Design Consultant, too!)

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 2301 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!


     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."



Tue, 02 Jul 1996 06:59:24 GMT  
 Learning VHDL

Quote:

>What you describe is what a lot of beginning VHDL users do to get up and
>running in the language.  (That is, they depend heavily on examples and
>they take sort of a "cut and paste" approach to using the language.  I've
>even had customers who've asked outright: "Could you just give me an
>example to do XYZ and I'll expand it to my application?")

>In my opinion and other VHDL users opinion this isn't really knowing the
>language but more like parroting the language.  

I disagree here. A logic designer should be *intimately* familiar with
that subset of the language that her synthesis tool uses. No parroting
here. Acquiring intimate familiarity does take more than 2 weeks, but my
point was that a new designer could start being productive inside 2
weeks in a design team that already has VHDL expertise. From this point
of view VHDL is no more difficult to learn than you said Verilog is.

I think that when they have reached expertise with their synthesizable
VHDL subset, most designers won't go on to learn the other features of
the language that enable one to model plate techtonics.

I've used VHDL at both high level and gate level. Based on my experience
we need some more language changes to aid very high level modelling. In
particular I'd like pointer signals or globally accessible access types
(or some other means to avoid passing huge data structures as function
parameters or inter block signals).

Mark
speaking for no-one.



Tue, 02 Jul 1996 07:42:40 GMT  
 Learning VHDL
: Just as a point of information, Aage, the Rule of Thumb in learning
: hardware description languages is that it takes about two weeks of
: intensive study to learn enough Verilog to be productive and about
: two months to learn VHDL to become productive.

A point of disagreement: its been my experience an EE with a brain
can pick up VHDL in under a week and produce useful code.  The stuff
that takes months to come to grips with (resolution functions etc) is
really not necessary for the average designer.

Martin.



Tue, 02 Jul 1996 15:27:45 GMT  
 Learning VHDL

Quote:

>: Just as a point of information, Aage, the Rule of Thumb in learning
>: hardware description languages is that it takes about two weeks of
>: intensive study to learn enough Verilog to be productive and about
>: two months to learn VHDL to become productive.

>A point of disagreement: its been my experience an EE with a brain
>can pick up VHDL in under a week and produce useful code.  The stuff
>that takes months to come to grips with (resolution functions etc) is
>really not necessary for the average designer.

Sorry John, but I have to agree with Martin.  I jumped into the middle of VHDL
about two years ago, and I was writing working synthesizable code about a
week later.  The synthesis subset of VHDL is only a very small part of the language,
especially if you want your VHDL to be generic enough to work on synthesis tools
from several vendors.

I didn't really have to learn "full" vhdl until I started debugging all of
these silly F22 "FBFM's" and started putting them together. At that point you
learn about passing generics, specifying types with full library path names,
and such other such ilk.

Now I'm faced with having to learn Verilog!

---
                            David Bishop


US MAIL:  RR2 Box 183A, Rome NY  13440  | not my company's.
PHYSICAL: 43.150N 75.414E 650'          |



Tue, 02 Jul 1996 21:52:28 GMT  
 Learning VHDL

Quote:

>Sorry John, but I have to agree with Martin.  I jumped into the middle of VHDL
>about two years ago, and I was writing working synthesizable code about a
>week later.  The synthesis subset of VHDL is only a very small part of the
>language, especially if you want your VHDL to be generic enough to work on
>synthesis tools from several vendors.

What you're talking about here is the parroting phenomina that I decribed
in an earlier post.  It's an age old trick where if you need to create a
file in any format, you find an example close to what you're looking for
and modify it to do your specific task.

Because Verilog is extremely C-like and most EE's have C experience, Verilog
is an easy language for them to use.  Because VHDL is extremely Ada-like
and most EE's have never even seen Ada, it takes a considerably larger ramp
up to be fluent in VHDL.

Quote:
>I didn't really have to learn "full" vhdl until I started debugging all of
>these silly F22 "FBFM's" and started putting them together. At that point you
>learn about passing generics, specifying types with full library path names,
>and such other such ilk.

Bingo!  Exactly what I'm talking about!

Quote:
>Now I'm faced with having to learn Verilog!

If you know C you'll find this fairly easy to do.  ;^)

It's not lost on me that there's a religious war going on between Verilog and
VHDL supporters.  In many cases it's gotten to the point where people can't
make even obvious statements about either language without drawing fire from a
particular language's supporters.  Please note: in ESNUG and in my consulting
business I use both VHDL and Verilog all the time.   I'd like to ask that
my observation about learning the two languages be taken in the spirit of
someone who lives in both camps.

As far as I'm concerned, whatever the customer *pays* you to work in is the
right HDL!  ;^)
                              - John Cooley
                                the ESNUG guy
                                (and EDA & ASIC Design Consultant, too!)

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 2301 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!


     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."



Wed, 03 Jul 1996 02:39:55 GMT  
 Learning VHDL

Quote:
> Because Verilog is extremely C-like and most EE's have C experience, Verilog
> is an easy language for them to use.  Because VHDL is extremely Ada-like
> and most EE's have never even seen Ada, it takes a considerably larger ramp
> up to be fluent in VHDL.

First of all, I have never seen a line of Verilog -- but, since this is
comp.lang.VHDL, I'm not supposed to either.  I have seen another,
FPGA-specific, HDL (that shall go nameless) with the "merit" of being
similar in syntax to Pascal, and I'm very sceptical about the value of this.

The novel user often will think "aha! - another Pascal compiler!" and just
continue programming in Pascal, understanding that this is not *exactly*
the same, but never really taking the time to study and understand the
(radically) different operational semantics.

From personal experience, I have seen a few 'average EE students' still
scratching their heads after several months of ?HDL practice talking like
"Hey, I only ever assign 3 or 6 to x -- how could it ever get to be 7?
This d*mn compiler is broken!"

Quote:
> What you're talking about here is the parroting phenomina that I decribed
> in an earlier post.  It's an age old trick where if you need to create a
> file in any format, you find an example close to what you're looking for
> and modify it to do your specific task.

True.  But the tricky part is, when the example that you copy from has the
right syntax but the wrong semantic content for your task -- i.e. when you
try to make your prime-number-generator-chip by tweaking your favourite
prime number program.  It's like learning to speak in a new language that
has the same words as your native language, only their meanings are
different.

Just another average CS point of view...

/Ole Sandum.
--



Wed, 03 Jul 1996 17:24:12 GMT  
 Learning VHDL

Quote:

>here. Acquiring intimate familiarity does take more than 2 weeks, but my
>point was that a new designer could start being productive inside 2
>weeks in a design team that already has VHDL expertise. From this point
>of view VHDL is no more difficult to learn than you said Verilog is.

 I agree with this wholeheartedly.  I created a heavy duty model in VHDL
 last summer without any prior knowledge of the language.  In fact, I was
 up and writing code in less than 2 weeks (and I'm not a software guy
 even!).

Quote:
>I think that when they have reached expertise with their synthesizable
>VHDL subset, most designers won't go on to learn the other features of
>the language that enable one to model plate techtonics.

 I agree, once again.  I used some really strange hacks to get certain things
 to work.  It's amazing what designers can do with this language and the best
 thing about it is that things like test benches are written in the same
 language as the design model and thus completely compatible.

-Krish

--

Krish



Thu, 04 Jul 1996 14:59:29 GMT  
 
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