Synthesizing RAM bank from VHDL? 
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 Synthesizing RAM bank from VHDL?


if you are using the ES2 process then they have macrocell compilers for RAM, DPRAM & FIFO. You specify, for example, the RAM size and it will return timing and area information plus a symbol and simulation model (verilog).

I assume that you will be using the Eurochip supplied design kit, if so the macrocell compilers will be included.


Sat, 18 Oct 1997 03:00:00 GMT  
 [ 1 post ] 

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