slow slew rate signal... 
Author Message
 slow slew rate signal...

I ran into a problem which drove me nuts but when I thought about it, it
made sense.

- I have a signal I am trying to monitor with a state machine
- The state machine runs at 25Mhz
- The signal to sample incoming comes through an opto coupler and has a slow
slew rate.
- If I sample the high slew clock at this fast rate the state machine
glitches.
- I understand (NOW!!) the state machine glitches because I sample while the
signal is in the undefined point anround half Vcc or whatever where the
input can't decided if it is low or high so sometimes 2 samples in here are
seen as high an low and thus my state machine glitches.

SOLUTIONS I CANT DO THAT WOULD WORK
1.) Put a schmidt trigger on the signal (requires board change)
2.) Slow the state machine down to go over the state machine

Can anyone think of a solution that I could implement in VHDL code so I
don't have to relay the board?

TIA Leon



Sat, 09 Apr 2005 22:48:59 GMT  
 slow slew rate signal...
Not absolutely sure what you mean by state machine glitches.
What is the slew rate of your incoming signal and what is the frequency of
this signal.
Additionaly I think you are facing a metastability problem.

If the frequency of your incoming signal is lower that the fsm's frequency
you can use a sync stage. Just use 2 ffs  in series to sample the incoming
data.
The output of your second ff can be used to feed the fsm. You can also use
these two ffs
for edge detection.

HTH

Ansgar

--
Attention please, reply address is invalid, please remove "_xxx_" ro reply



Quote:
> I ran into a problem which drove me nuts but when I thought about it, it
> made sense.

> - I have a signal I am trying to monitor with a state machine
> - The state machine runs at 25Mhz
> - The signal to sample incoming comes through an opto coupler and has a
slow
> slew rate.
> - If I sample the high slew clock at this fast rate the state machine
> glitches.
> - I understand (NOW!!) the state machine glitches because I sample while
the
> signal is in the undefined point anround half Vcc or whatever where the
> input can't decided if it is low or high so sometimes 2 samples in here
are
> seen as high an low and thus my state machine glitches.

> SOLUTIONS I CANT DO THAT WOULD WORK
> 1.) Put a schmidt trigger on the signal (requires board change)
> 2.) Slow the state machine down to go over the state machine

> Can anyone think of a solution that I could implement in VHDL code so I
> don't have to relay the board?

> TIA Leon



Sat, 09 Apr 2005 22:55:42 GMT  
 slow slew rate signal...
Leon,
    A few ideas...
1.     Can you oversample the data in some fashion and then look for more
that just 1 changed bit?
2.    Can you use a different type of opto-coupler such as one with either a
higher gain or a built-in Schmidt trigger?
3.    Depending on the configuration could you use a non-opto isolator such
as the iso-loop parts from nve corp? http://www.nve.com  (I have used these
at 100 megabaud and they are available from Digikey.  Cost seems to be
reasonable given Digikey as a distributor.)

Theron



Quote:
> I ran into a problem which drove me nuts but when I thought about it, it
> made sense.

> - I have a signal I am trying to monitor with a state machine
> - The state machine runs at 25Mhz
> - The signal to sample incoming comes through an opto coupler and has a
slow
> slew rate.
> - If I sample the high slew clock at this fast rate the state machine
> glitches.
> - I understand (NOW!!) the state machine glitches because I sample while
the
> signal is in the undefined point anround half Vcc or whatever where the
> input can't decided if it is low or high so sometimes 2 samples in here
are
> seen as high an low and thus my state machine glitches.

> SOLUTIONS I CANT DO THAT WOULD WORK
> 1.) Put a schmidt trigger on the signal (requires board change)
> 2.) Slow the state machine down to go over the state machine

> Can anyone think of a solution that I could implement in VHDL code so I
> don't have to relay the board?

> TIA Leon



Sat, 09 Apr 2005 23:09:41 GMT  
 slow slew rate signal...
Leon,

You are completely correct in your assesment of what is happening.

One way to deal with slow rising signals that may have noise on them is to add
states to the state machine.  If it senses a 'high', it then goes to a "check
that it is really going high+1" state where on the next state machine clock, it
checks again to see if it is still high.  One might have to add as many as 128
checks (or more) for high, or low, depending on the state machine clock rate,
and the rise and fall times of the slow signal.

If any sample disagrees, then the state returns to the beginning where it starts
all over checking for a change.

Austin

Quote:

> I ran into a problem which drove me nuts but when I thought about it, it
> made sense.

> - I have a signal I am trying to monitor with a state machine
> - The state machine runs at 25Mhz
> - The signal to sample incoming comes through an opto coupler and has a slow
> slew rate.
> - If I sample the high slew clock at this fast rate the state machine
> glitches.
> - I understand (NOW!!) the state machine glitches because I sample while the
> signal is in the undefined point anround half Vcc or whatever where the
> input can't decided if it is low or high so sometimes 2 samples in here are
> seen as high an low and thus my state machine glitches.

> SOLUTIONS I CANT DO THAT WOULD WORK
> 1.) Put a schmidt trigger on the signal (requires board change)
> 2.) Slow the state machine down to go over the state machine

> Can anyone think of a solution that I could implement in VHDL code so I
> don't have to relay the board?

> TIA Leon



Sat, 09 Apr 2005 23:10:28 GMT  
 slow slew rate signal...

Quote:

> - I have a signal I am trying to monitor with a state machine
> - The state machine runs at 25Mhz
> - The signal to sample incoming comes through an opto coupler and has a slow
> slew rate.
> - If I sample the high slew clock at this fast rate the state machine
> glitches.

Consider synchronizing all inputs to the state machine to the 25Mhz clock.

     -- Mike Treseler



Sat, 09 Apr 2005 23:36:08 GMT  
 slow slew rate signal...
I support Austin's idea of filtering the input signal with a digital low-pass
filter.
But there may also be another solution.
You don't like to add a Schmitt trigger because that would change the pc-board.

Well, it doesn't have to.
Depending on the output impedance of your optocoupler, you can achieve
Schmitt-trigger performance if you drive the input signal non-inverted back
onto the same pin. Make the output drive as week as you can ( 2 mA) which means
about 100 to 200 Ohm.
If the optocoupler output impedance is in the 50 to 100 Ohm range, you might
have a nice hysteresis on the input...

Peter Alfke
=================

Quote:

> I ran into a problem which drove me nuts but when I thought about it, it
> made sense.

> - I have a signal I am trying to monitor with a state machine
> - The state machine runs at 25Mhz
> - The signal to sample incoming comes through an opto coupler and has a slow
> slew rate.
> - If I sample the high slew clock at this fast rate the state machine
> glitches.
> - I understand (NOW!!) the state machine glitches because I sample while the
> signal is in the undefined point anround half Vcc or whatever where the
> input can't decided if it is low or high so sometimes 2 samples in here are
> seen as high an low and thus my state machine glitches.

> SOLUTIONS I CANT DO THAT WOULD WORK
> 1.) Put a schmidt trigger on the signal (requires board change)
> 2.) Slow the state machine down to go over the state machine

> Can anyone think of a solution that I could implement in VHDL code so I
> don't have to relay the board?

> TIA Leon



Sat, 09 Apr 2005 23:55:22 GMT  
 slow slew rate signal...


Quote:
> I support Austin's idea of filtering the input signal with a digital
low-pass
> filter.

I would go for the digital low pass filter. Make a shift register, lets say
4 bits. Shift you input sinal into this register. Then another (5th)
FlipFLop is loaded with '1', when the register is "1111", and with "0" wheh
the register is "0000", all other codes of the register leave the state of
the FlipFlop unaltered.

In VHDL this looks like this.

signal shift : std_logic_vector (3 downto 0);
signal clean_input : std_logic;

process(clk25MHz)
begin
  if clk25MHz=1 and clk25MHz'event then
    shift <= shift(2 downto 0) & data_from_opto;
    if shift="0000" then
      clean_signal <='0';
    elsif shift="1111" then
       clean_signal <= '1';
    end if;
  end if;
end process;

The shift register should be long enough to cover the whole rise/fall time
of the signal, e.g. if the rise/fall time is 1us (sloooooow), then it must

--
MfG
Falk



Sun, 10 Apr 2005 01:01:09 GMT  
 slow slew rate signal...

Quote:

> I ran into a problem which drove me nuts but when I thought about it, it
> made sense.

> - I have a signal I am trying to monitor with a state machine
> - The state machine runs at 25Mhz
> - The signal to sample incoming comes through an opto coupler and has a slow
> slew rate.
> - If I sample the high slew clock at this fast rate the state machine
> glitches.
> - I understand (NOW!!) the state machine glitches because I sample while the
> signal is in the undefined point anround half Vcc or whatever where the
> input can't decided if it is low or high so sometimes 2 samples in here are
> seen as high an low and thus my state machine glitches.

 Correct - when running state machines from async IPs ( including those
with perfect rise times ) it is important to avoid aperture effects,
where more than one State Bit depends on the IP at a given time.
 Whilst it is possible to code such state machines, it can be much
simpler to add at least one syncronising flip-flop to the IP.

 An additional voting noise filter can help, esp if the state engine
actually
has a MIN HI or LOW requirement - many do, and you should check what
your
effective Fmax IP is, and design a noise filter/vote scheme to keep
under that.

 The Shift register + Sticky Bit filter idea already proposed is a good
one.

Quote:

> SOLUTIONS I CANT DO THAT WOULD WORK
> 1.) Put a schmidt trigger on the signal (requires board change)
> 2.) Slow the state machine down to go over the state machine

> Can anyone think of a solution that I could implement in VHDL code so I
> don't have to relay the board?

 For testing, add a Schmitt to the path
( eg Schmitt opto H11L1/better, or TinylLogic 1G17 ) and check
it actually works 100.00%
 Apply the coding changes, until it worka 100.00%, then remove the
schmitt,
and check it is still OK.

-jg



Sun, 10 Apr 2005 02:40:30 GMT  
 slow slew rate signal...


Quote:
>I support Austin's idea of filtering the input signal with a digital low-pass
>filter.
>But there may also be another solution.
>You don't like to add a Schmitt trigger because that would change the pc-board.

>Well, it doesn't have to.
>Depending on the output impedance of your optocoupler, you can achieve
>Schmitt-trigger performance if you drive the input signal non-inverted back
>onto the same pin. Make the output drive as week as you can ( 2 mA) which means
>about 100 to 200 Ohm.
>If the optocoupler output impedance is in the 50 to 100 Ohm range, you might
>have a nice hysteresis on the input...

Alternatively, since opto-couplers are usually open collector style
outputs... is it just the rising edge (controlled by a pull-up resistor)
or also the falling edge that cause problems?

The state machine could go through intermediate states ( filtering the
input as others have suggested) ... in the first intermediate state it
could enable its output buffer to accelerate the rise time (and/or fall
time) through the transition region, then disable the output again until
the next detected rising (and/or falling) edge.

- Brian



Sun, 10 Apr 2005 21:34:46 GMT  
 slow slew rate signal...
Hi Leon,

As others have mentioned use a simple majority voting system to
de-bounce your slow changing input

ie. (approximate VHDL)

Process  (clock, reset)
delayedsignal_1 <= input;           --this happens on the first clock
delayedsignal_2 <= delayedsignal_1; --this happens on the next clock
delayedsignal_3 <= delayedsignal_2; --and this on the next
delayedsignal_4 <= delayedsignal_3; -- etc
delayedsignal_5 <= delayedsignal_4;
....
....

if delayedsignal_1 = '1' and delayedsignal_2='1' and ........
         then output<='1'; --when they are all 1 you get 1

elsif delayedsignal_1 = '0' and delayedsignal_2='0' and ........
         then output<='0'; --when they are all 0 you get 0

else null; --make a latch  --otherwise it remembers
end if;

end process

If you like you can make a slow clock using the excellent clock
divider in the FAQ pages. Use this slow clock in the above process and
then the signals can be as slow as you like.

I've found with state machines you have to register all the inputs and
all the outputs or else you get glitches.

Best of Luck

Phil



Sun, 10 Apr 2005 22:55:43 GMT  
 slow slew rate signal...
   No it's not metastability, this problem would exist on even normal logic
not only FPGA's. Lets say I am dealing with 3V logic in which a low is
anything below 1 volt and a high anything above 2 volts. So what happens if
I have a 1.5V signal? Well it could go to either level. Okay lets say for
arguement that because it can't decide 50% of the time it reports as high
and 50% low.

   Now lets say I have a slow slew signal that takes 3uS to slew from 0V to
3V. For 1uS the signal will be definitely low, for 1uS the signal will be in
this 50/50 undefined area and for 1uS the signal will be high. Now lets
sample this signal at 10Mhz which means I get 10 samples for every 1uS. The
first 10 samples in the 1uS while the signal is low will be low. The last 10
samples in the 1uS while the signal is high will be high. But the middle 1uS
in the 50/50 zone will return random samples so lets say it returns the
following HLLHHLLHHL for its ten samples based on 50/50 probability of high
or low

So my sampled signal looks like

LLLLLLLLLL HLLHHLLHHL  HHHHHHHHHH
{ 10 samples } { 10 samples    } { 10 Samples }
{ low period }  { 50/50 period } { high period }

Remember ignoring the slew the signal was
LLLLLLLLLLLLLLLLLHHHHHHHHHHHHHH

In the 50/50 zone (which is not a stable input level) multiple sampling will
cause extra pulses and thus any attempt to use with a state machine these
false edges will glitch the state machine.


Quote:
> Not absolutely sure what you mean by state machine glitches.
> What is the slew rate of your incoming signal and what is the frequency of
> this signal.
> Additionaly I think you are facing a metastability problem.

> If the frequency of your incoming signal is lower that the fsm's frequency
> you can use a sync stage. Just use 2 ffs  in series to sample the incoming
> data.
> The output of your second ff can be used to feed the fsm. You can also use
> these two ffs
> for edge detection.

> HTH

> Ansgar

> --
> Attention please, reply address is invalid, please remove "_xxx_" ro reply



> > I ran into a problem which drove me nuts but when I thought about it, it
> > made sense.

> > - I have a signal I am trying to monitor with a state machine
> > - The state machine runs at 25Mhz
> > - The signal to sample incoming comes through an opto coupler and has a
> slow
> > slew rate.
> > - If I sample the high slew clock at this fast rate the state machine
> > glitches.
> > - I understand (NOW!!) the state machine glitches because I sample while
> the
> > signal is in the undefined point anround half Vcc or whatever where the
> > input can't decided if it is low or high so sometimes 2 samples in here
> are
> > seen as high an low and thus my state machine glitches.

> > SOLUTIONS I CANT DO THAT WOULD WORK
> > 1.) Put a schmidt trigger on the signal (requires board change)
> > 2.) Slow the state machine down to go over the state machine

> > Can anyone think of a solution that I could implement in VHDL code so I
> > don't have to relay the board?

> > TIA Leon



Mon, 11 Apr 2005 00:01:49 GMT  
 slow slew rate signal...
Oversampling is what I currently have anyhow.
The other ideas will work but I don't want to s{*filter*}the board I have done.


Quote:
> Leon,
>     A few ideas...
> 1.     Can you oversample the data in some fashion and then look for more
> that just 1 changed bit?
> 2.    Can you use a different type of opto-coupler such as one with either
a
> higher gain or a built-in Schmidt trigger?
> 3.    Depending on the configuration could you use a non-opto isolator
such
> as the iso-loop parts from nve corp? http://www.*-*-*.com/  (I have used
these
> at 100 megabaud and they are available from Digikey.  Cost seems to be
> reasonable given Digikey as a distributor.)

> Theron



> > I ran into a problem which drove me nuts but when I thought about it, it
> > made sense.

> > - I have a signal I am trying to monitor with a state machine
> > - The state machine runs at 25Mhz
> > - The signal to sample incoming comes through an opto coupler and has a
> slow
> > slew rate.
> > - If I sample the high slew clock at this fast rate the state machine
> > glitches.
> > - I understand (NOW!!) the state machine glitches because I sample while
> the
> > signal is in the undefined point anround half Vcc or whatever where the
> > input can't decided if it is low or high so sometimes 2 samples in here
> are
> > seen as high an low and thus my state machine glitches.

> > SOLUTIONS I CANT DO THAT WOULD WORK
> > 1.) Put a schmidt trigger on the signal (requires board change)
> > 2.) Slow the state machine down to go over the state machine

> > Can anyone think of a solution that I could implement in VHDL code so I
> > don't have to relay the board?

> > TIA Leon



Mon, 11 Apr 2005 00:03:05 GMT  
 slow slew rate signal...
That will work.
All I have to do is work out how many samples is need to exceed the maximum
slew time.

Thanks


Quote:
> Leon,

> You are completely correct in your assesment of what is happening.

> One way to deal with slow rising signals that may have noise on them is to
add
> states to the state machine.  If it senses a 'high', it then goes to a
"check
> that it is really going high+1" state where on the next state machine
clock, it
> checks again to see if it is still high.  One might have to add as many as
128
> checks (or more) for high, or low, depending on the state machine clock
rate,
> and the rise and fall times of the slow signal.

> If any sample disagrees, then the state returns to the beginning where it
starts
> all over checking for a change.

> Austin


> > I ran into a problem which drove me nuts but when I thought about it, it
> > made sense.

> > - I have a signal I am trying to monitor with a state machine
> > - The state machine runs at 25Mhz
> > - The signal to sample incoming comes through an opto coupler and has a
slow
> > slew rate.
> > - If I sample the high slew clock at this fast rate the state machine
> > glitches.
> > - I understand (NOW!!) the state machine glitches because I sample while
the
> > signal is in the undefined point anround half Vcc or whatever where the
> > input can't decided if it is low or high so sometimes 2 samples in here
are
> > seen as high an low and thus my state machine glitches.

> > SOLUTIONS I CANT DO THAT WOULD WORK
> > 1.) Put a schmidt trigger on the signal (requires board change)
> > 2.) Slow the state machine down to go over the state machine

> > Can anyone think of a solution that I could implement in VHDL code so I
> > don't have to relay the board?

> > TIA Leon



Mon, 11 Apr 2005 00:05:29 GMT  
 slow slew rate signal...
They are synchronized the 25Mhz is the system clock that's the reason for
sampling with the thing. That's not the issue the slew through the undefined
logic levels is the problem.


Quote:

> > - I have a signal I am trying to monitor with a state machine
> > - The state machine runs at 25Mhz
> > - The signal to sample incoming comes through an opto coupler and has a
slow
> > slew rate.
> > - If I sample the high slew clock at this fast rate the state machine
> > glitches.

> Consider synchronizing all inputs to the state machine to the 25Mhz clock.

>      -- Mike Treseler



Mon, 11 Apr 2005 00:06:49 GMT  
 slow slew rate signal...
Yep that would work, not elegant but it would work. You are biasing the
input so in the undefined zone it goes to the current output level.


Quote:
> I support Austin's idea of filtering the input signal with a digital
low-pass
> filter.
> But there may also be another solution.
> You don't like to add a Schmitt trigger because that would change the
pc-board.

> Well, it doesn't have to.
> Depending on the output impedance of your optocoupler, you can achieve
> Schmitt-trigger performance if you drive the input signal non-inverted
back
> onto the same pin. Make the output drive as week as you can ( 2 mA) which
means
> about 100 to 200 Ohm.
> If the optocoupler output impedance is in the 50 to 100 Ohm range, you
might
> have a nice hysteresis on the input...

> Peter Alfke
> =================

> > I ran into a problem which drove me nuts but when I thought about it, it
> > made sense.

> > - I have a signal I am trying to monitor with a state machine
> > - The state machine runs at 25Mhz
> > - The signal to sample incoming comes through an opto coupler and has a
slow
> > slew rate.
> > - If I sample the high slew clock at this fast rate the state machine
> > glitches.
> > - I understand (NOW!!) the state machine glitches because I sample while
the
> > signal is in the undefined point anround half Vcc or whatever where the
> > input can't decided if it is low or high so sometimes 2 samples in here
are
> > seen as high an low and thus my state machine glitches.

> > SOLUTIONS I CANT DO THAT WOULD WORK
> > 1.) Put a schmidt trigger on the signal (requires board change)
> > 2.) Slow the state machine down to go over the state machine

> > Can anyone think of a solution that I could implement in VHDL code so I
> > don't have to relay the board?

> > TIA Leon



Mon, 11 Apr 2005 00:09:39 GMT  
 
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