question about signal assignment in "case" 
Author Message
 question about signal assignment in "case"

Hi guys,

I wonder if both of the following codes are okay, especially the first one.
Thank you!

----------------------------------------------------------------------------
------------------------------
-- 1st:
    case current_state is
      when S0 =>      mux_sel <= "01" when (jump = '1') else "00";        --
not sure about the "00" part.
      when S1 =>      mux_sel <= "10";
      when others => null;
   end case;

-- 2nd:
    case current_state is
      when S0 =>      if (jump = '1') then
                                mux_sel <= "01";
                             end if;
      when S1 =>      mux_sel <= "10";
      when others => null;
   end case;



Thu, 08 Jan 2004 15:56:15 GMT  
 question about signal assignment in "case"
Hi jeff
I think both code should work the same. In the first case you are
using the conditional assignment whereas in second case you are
caarrying out sequential signal assignment.
thats it!

sandeep

Quote:

> Hi guys,

> I wonder if both of the following codes are okay, especially the first one.
> Thank you!

> ----------------------------------------------------------------------------
> ------------------------------
> -- 1st:
>     case current_state is
>       when S0 =>      mux_sel <= "01" when (jump = '1') else "00";        --
> not sure about the "00" part.
>       when S1 =>      mux_sel <= "10";
>       when others => null;
>    end case;

> -- 2nd:
>     case current_state is
>       when S0 =>      if (jump = '1') then
>                                 mux_sel <= "01";
>                              end if;
>       when S1 =>      mux_sel <= "10";
>       when others => null;
>    end case;



Thu, 08 Jan 2004 22:59:48 GMT  
 question about signal assignment in "case"

Quote:
> -- 1st:
>     case current_state is
>       when S0 =>      mux_sel <= "01" when (jump = '1') else
      --
> not sure about the "00" part.
>       when S1 =>      mux_sel <= "10";
>       when others => null;
>    end case;

Not ok. The conditional assignment with 'when' is only allowed as a
concurrent statement, not as a sequential statement.

Quote:
> -- 2nd:
>     case current_state is
>       when S0 =>      if (jump = '1') then
>                                 mux_sel <= "01";
>                              end if;
>       when S1 =>      mux_sel <= "10";
>       when others => null;
>    end case;

This is correct VHDL, but if these are the only assignments to mux_sel in
the process, then you will create a latch for mux_sel: when current_state =
S0 and jump /= '1', then mux_sel is not assigned value.

Tom



Fri, 09 Jan 2004 02:47:26 GMT  
 question about signal assignment in "case"
Hi Tom,

I think you are right. But do you mean a latch is what I should avoid?
Should I insert "else" behind the "if"? Actually, I have a bunch of signals
that needs "if..elsif/else..end if" to assign value in EVERY "when". Do you
think it's okay to use "repeated but a little bit different" statements in
every "when"? The whole VHDL is like below (didn't modify the conditional
statements yet). Thank you guys so much!

Jeff

---------------------------------------------------------------
  case current_state is
      when S0 =>
        if di_op = '1' then
          s_int_enable <= '0';
        elsif (ei_op = '1' and brc_op = '0' and jmp_op = '0'
               and jal_op = '0') or reset = '1' then
          s_int_enable <= '1';
        end if;
        mux_sel <= "01" when (jal_op = '1') else "00";
        chg_pc <= '1' when ((brc_op = '1') and (int_cnd = '1')) or
            (jal_op = '1') or (jmp_op = '1') else '0';
        kill <= '1' when ((brc_op = '1') or (jmp_op = '1')) else '0';
        bu_addl_en <= '1' when((brc_op = '1') or (jmp_op = '1')
                 or (jal_op = '1')) else '0';
        eoi < = '1';
        mux_int_en <= '0';

      when S1 =>
        s_int_enable <= '0';
        mux_sel < = "10";
        bu_addl_en <= '1';
        eoi <= '0';
        kill <= '1';
        chg_pc < = '1';
        mux_int_en <= '1';

      when S2 =>
        s_int_enable <= '0';
        mux_sel < = "00";
        bu_addl_en <= '0';
        eoi <= '0';
        kill <= '1';
        chg_pc <= '0';
        mux_int_en <= '0';

      when S3 =>
        s_int_enable <= '0';
        eoi < = '0';
        mux_sel <= "01" when (jal_op = '1') else "00";
        chg_pc <= '1' when ((brc_op = '1') and (int_cnd = '1')) or
            (jal_op = '1') or (jmp_op = '1') else '0';
        kill <= '1' when ((brc_op = '1') or (jmp_op = '1')
            or (reti_op = '1')) else '0';
        bu_addl_en <= '1' when((brc_op = '1') or (jmp_op = '1')
            or (jal_op = '1')) else '0';
        mux_int_en <= '0';

      when others => null;

    end case;

"Tom Verbeure"

Quote:

> > -- 1st:
> >     case current_state is
> >       when S0 =>      mux_sel <= "01" when (jump = '1') else
>       --
> > not sure about the "00" part.
> >       when S1 =>      mux_sel <= "10";
> >       when others => null;
> >    end case;

> Not ok. The conditional assignment with 'when' is only allowed as a
> concurrent statement, not as a sequential statement.

> > -- 2nd:
> >     case current_state is
> >       when S0 =>      if (jump = '1') then
> >                                 mux_sel <= "01";
> >                              end if;
> >       when S1 =>      mux_sel <= "10";
> >       when others => null;
> >    end case;

> This is correct VHDL, but if these are the only assignments to mux_sel in
> the process, then you will create a latch for mux_sel: when current_state
=
> S0 and jump /= '1', then mux_sel is not assigned value.

> Tom



Fri, 09 Jan 2004 04:23:18 GMT  
 question about signal assignment in "case"

Quote:

> Hi Tom,

> I think you are right. But do you mean a latch is what I should avoid?
> Should I insert "else" behind the "if"? Actually, I have a bunch of signals

You could use a "default" that will be overriden in the case-sequence if
necessary
e.g.

out1<='0';
out2<='0';

Case ...
   when ... => out1<='1';
   when ... => out2<='1';
 ....

if the two assignments '0' and '1' occure for the same time, the second
will override the first.

bye Thomas

--
Thomas Stanka      
Bosch SatCom GmbH           UC_RA/EMD4 s/UC-RA/BC
Gerberstr. 49              Tel. +49 7191 930-1690
Zi. 10/528                Fax. +49 7191 930-21690      



Fri, 09 Jan 2004 14:39:59 GMT  
 
 [ 5 post ] 

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