This question recently came up in our research group:
How could you do profiling natively in VHDL?

Idea: You have a hierarchical model structure, which is on the lowest
level described by behavioural architectures which contain processes.
Assume you want statistics on how often the processes are executed
during a simulation run.
So you add a signal in each architecture embedding processes for
each process and a line in each process that increments this signal
when a process is triggered.

And then: how would you transport this data to the outer world?
An idea would be a package that has a shared variable (list of record
elements) and an impure function 'add_entry_to_list' that writes to the
shared variable in the package (and another one that for instance dequeues
that variable into a textio file).

Any architecture which has processes to profile would then have a use
clause declaring this profiling package. The question is now: is the body
of such a package guaranteed to be instantiated only once, so that I do not
have multiple instances of such a shared variable floating around in
the elaborated model?

Or, if not, how would one solve this in VHDL?

(Of course, this relates to VHDL'93 as 87 lacks shared variables).

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