What to be included in sensitivity list? 
Author Message
 What to be included in sensitivity list?

Can somebody tell me the difference in effect between the following
two processes (look at the sensitivity list):-

process(clk)
begin
    if rst='1' then
        q<='0';
    elsif (clk'event and clk='1') then
        q<=d;
    end if;
end process;

process(rst, clk)
begin
    if rst='1' then
        q<='0';
    elsif (clk'event and clk='1') then
        q<=d;
    end if;
end process;

I have seen both from different books and I am getting confused
about which is the right code I am suppose to stick with.

Thanks for any help.

C. Fung,



Sun, 27 Jan 2002 03:00:00 GMT  
 What to be included in sensitivity list?

Quote:

> Can somebody tell me the difference in effect between the following
> two processes (look at the sensitivity list):-

> process(clk)
> begin
>     if rst='1' then
>         q<='0';
>     elsif (clk'event and clk='1') then
>         q<=d;
>     end if;
> end process;

> process(rst, clk)
> begin
>     if rst='1' then
>         q<='0';
>     elsif (clk'event and clk='1') then
>         q<=d;
>     end if;
> end process;

> I have seen both from different books and I am getting confused
> about which is the right code I am suppose to stick with.

> Thanks for any help.

> C. Fung,

The difference is the following, the process is always restarted when an
event occurs on a signal mentioned in the sensitivity list, in your case
that means the first process is reseted when 'rst' is '1' when an event
on 'clk' occurs (both edges) that means you have somewhat of synchronos
reset, the second process is started either with an event on 'rst' or on
'clk' that means the process is always reseted when rst goes to '1',
this reset is asynchronosly.

Regards,

--
------------------------------------------
Dirk-Rolf Aust, Design Engineer

mikron AG
Am Soeldnermoos 17
D-85399 Hallbergmoos
Germany

Tel: +49-(0)811-5539-106
FAX: +49-(0)811-5539-413
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Sun, 27 Jan 2002 03:00:00 GMT  
 What to be included in sensitivity list?

Quote:

> Can somebody tell me the difference in effect between the following
> two processes (look at the sensitivity list):-

> process(clk)
> begin
>     if rst='1' then
>         q<='0';
>     elsif (clk'event and clk='1') then
>         q<=d;
>     end if;
> end process;

> process(rst, clk)
> begin
>     if rst='1' then
>         q<='0';
>     elsif (clk'event and clk='1') then
>         q<=d;
>     end if;
> end process;

If you're looking for async reset registers the second process is the
one to go for - process is triggered by both reset and clock

If you're looking for sync reset registers use the following
process form - the reset vakue is only checked on the positive
clock edge

process(clk)
begin
    if (clk'event and clk='1') then
      if rst='1' then
        q<='0';
      else
        q<=d;
     end if;
  end if;
end process;

Since your first process is only triggered on a clock event,
it implies registers which are synchronously
reset on any clock event - i.e. both positive & negative
clock edges - but only update on a positive edge....

B

Esperan Ltd
The World's Leading HDL and FPGA Training Company
www.esperan.com



Sun, 27 Jan 2002 03:00:00 GMT  
 What to be included in sensitivity list?

Quote:

> Can somebody tell me the difference in effect between the following
> two processes (look at the sensitivity list):-

> process(clk)
> begin
>    if rst='1' then
>         q<='0';
>     elsif (clk'event and clk='1') then
>         q<=d;
>     end if;
> end process;

> process(rst, clk)
> begin
>     if rst='1' then
>         q<='0';
>     elsif (clk'event and clk='1') then
>         q<=d;
>     end if;
> end process;

> I have seen both from different books and I am getting confused
> about which is the right code I am suppose to stick with.

> Thanks for any help.

> C. Fung,

Here's another way to think about the sensitivity list (which is different than
the other explanations on this thread).  A 'process' is always handled in
sequential order...meaning that it is evaluated from top to bottom like a 'C' or
BASIC program.  However, it isn't continuously evaluated.  It's only evaluated
when there is a change (or edge) on one of the signals in the sensitivity list.

--
Wade D. Peterson
Silicore Corporation
3525 E. 27th St. No. 301, Minneapolis, MN USA 55406
TEL: (612) 722-3815, FAX: (612) 722-5841



Sun, 27 Jan 2002 03:00:00 GMT  
 What to be included in sensitivity list?

Quote:

> Can somebody tell me the difference in effect between the following
> two processes (look at the sensitivity list):-

> process(clk)
> begin
>     if rst='1' then
>         q<='0';
>     elsif (clk'event and clk='1') then
>         q<=d;
>     end if;
> end process;

This is illegal for synthesis and should generate an error. If not the
error checking is not very good in the synthesiser. It appears to
describe a register which can be reset sort-of-synchronously on both
clock edges. When reset is disabled it acts as a standard register. I
don't know of any registers that reset on both clock edges. It is in
fact a mistake and should read as your second example:

Quote:
> process(rst, clk)
> begin
>     if rst='1' then
>         q<='0';
>     elsif (clk'event and clk='1') then
>         q<=d;
>     end if;
> end process;

This is a proper template for an asynchronously resettable register. See
VHDL Question - Resets


Mon, 28 Jan 2002 03:00:00 GMT  
 What to be included in sensitivity list?
Andy makes an excellent point, the 1st code example is a poor
representation of a real life (sythesizable) circuit. At a minimum, a
good synthesis tool would give you some kind of warning regarding an
incomplete sensitivity list. In this case the main concern is what does
the tool do next  ... assume completeness (i.e. synthesize a flop with
async reset) ... or something else ??

To ensure that you get the desired synthesis results, use one of the
standard templates (previously posted in this thread) for asynchronous
or synchronous reset, depending on the desired configuration :

FOR ASYNCHRONOUS RESET USE:
---------------------------
 process(clk, rst)
 begin
     if rst='1' then                    -- rst='0' for active low rst
         q<='0';                    
     elsif (clk'event and clk='1') then -- clk='0' for falling edge
triggered
         q<=d;
     end if;
 end process;

FOR SYNCHRONOUS RESET USE:
--------------------------
process(clk)
begin
    if (clk'event and clk='1') then     -- clk='0' for falling edge
triggered
      if rst='1' then                   -- rst='0' for active low rst
        q<='0';
      else
        q<=d;
     end if;
  end if;
end process;

use the follwing templete

Quote:


> > Can somebody tell me the difference in effect between the following
> > two processes (look at the sensitivity list):-

> > process(clk)
> > begin
> >     if rst='1' then
> >         q<='0';
> >     elsif (clk'event and clk='1') then
> >         q<=d;
> >     end if;
> > end process;

> This is illegal for synthesis and should generate an error. If not the
> error checking is not very good in the synthesiser. It appears to
> describe a register which can be reset sort-of-synchronously on both
> clock edges. When reset is disabled it acts as a standard register. I
> don't know of any registers that reset on both clock edges. It is in
> fact a mistake and should read as your second example:

> > process(rst, clk)
> > begin
> >     if rst='1' then
> >         q<='0';
> >     elsif (clk'event and clk='1') then
> >         q<=d;
> >     end if;
> > end process;

> This is a proper template for an asynchronously resettable register.
> See VHDL Question - Resets



Wed, 30 Jan 2002 03:00:00 GMT  
 
 [ 6 post ] 

 Relevant Pages 

1. Sensitivity lists (activation lists)

2. Detecting missing signals in sensitivity lists

3. sensitivity list for clocked flops with async reset

4. Incomplete sensitivity lists

5. Sensitivity lists in latches

6. process sensitivity list

7. process sensitivity list question

8. simulation/synthesis implications of having only CLK in sensitivity list

9. Question about use of sensitivity list

10. I don't think sensitivity list of a process is necessary

11. Automatic insertion of signals to process sensitivity list

12. Beginner: When Others & Sensitivity List Questions

 

 
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