C language to VHDL Translation 
Author Message
 C language to VHDL Translation

Is anyone aware of a tool that provide a translation from C source to VHDL?
The intent would be to eventually provide a sythesis path for modules that
that we must currently construct in C language to be compatible with our
systems level simulator.


Mon, 29 Jan 1996 22:39:44 GMT  
 C language to VHDL Translation

Does anybody know of a systems level simulator that is based on VHDL ?
Now it seems that different simulators have different requirements on
how to create the models (and sometimes the model will behave differently
if you change platform but use the same tool ...).

And a VHDL-based tool would allow you to incorporate your existing RTL-level
VHDL models in the simulation, which would save the effort and error risk of
writing a new one in C.

Or are the any drawbacks with a VHDL-based systems level simulator ?

--


ESTEC WDN                 European Space Agency Technology Centre



Tue, 30 Jan 1996 00:42:54 GMT  
 
 [ 2 post ] 

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