reading files in VHDL / vsim 
Author Message
 reading files in VHDL / vsim

Hi all.  I'm trying to write a vhdl entity to help me run a
whole bunch of test_vectors to test the functionality of my
code.  Right now, I'm just trying to read a file correctly.
This is my code:

Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity test_module is
  port( data_vector : out std_logic_vector(0 to 9);
        clk : in std_logic);
end;

architecture testing of test_module is
begin
  process(clk)
    type ten_bit_vector is file of std_logic_vector(0 to 9);
    variable data_read : std_logic_vector(0 to 9);
    file data_file: ten_bit_vector is in
        "/u/rsf/code/vhdl/vectors/test_1.txt";
    begin
        read(data_file, data_read);
        data_vector <= data_read;
  end process;
end testing

I'm trying to read in bit vectors and ouput them to
data_vector.
This is the contents of text_1.txt:
0000011111
1111100000
0000000000
1111111111

This pretty much spits out garbage.  Is there a special
format files have to be in to read them into vhdl?  I'm
guessing my problem may be that test_1.txt is an ascii
file.  If this is a formating problem, how can I generate
the correct file format?

FYI - My goal is to use this with vsim/modeltech 5.3 so I
can test a series of test_vectors without typing the bit
vectors in by hand.  Does vsim have any features that will
allow me to do this without writing this extra code.

Thanks in advance for any help you can provide.
-Swope

* Sent from AltaVista http://www.*-*-*.com/ Where you can also find related Web Pages, Images, Audios, Videos, News, and Shopping.  Smart is Beautiful



Fri, 31 Jan 2003 03:00:00 GMT  
 reading files in VHDL / vsim
Swope,
  What you are doing is correct if the data file was written in a binary format that model tech support.  If you have plain text files then use the textio
package you will need the standard version and to make life easier also the synopsys modified std_logic_textio package.  The method that you are currently
using is correct but the file is not in the binary format so you will get out garbage.

Another option is to write a script to transform the input vectors to forces at the specified time and use this new file as a "do" file.  That just one
option.

Craig

Quote:

> Hi all.  I'm trying to write a vhdl entity to help me run a
> whole bunch of test_vectors to test the functionality of my
> code.  Right now, I'm just trying to read a file correctly.
> This is my code:

> Library IEEE;
> use IEEE.std_logic_1164.all;
> use IEEE.std_logic_unsigned.all;
> use IEEE.std_logic_arith.all;

> entity test_module is
>   port( data_vector : out std_logic_vector(0 to 9);
>         clk : in std_logic);
> end;

> architecture testing of test_module is
> begin
>   process(clk)
>     type ten_bit_vector is file of std_logic_vector(0 to 9);
>     variable data_read : std_logic_vector(0 to 9);
>     file data_file: ten_bit_vector is in
>         "/u/rsf/code/vhdl/vectors/test_1.txt";
>     begin
>         read(data_file, data_read);
>         data_vector <= data_read;
>   end process;
> end testing

> I'm trying to read in bit vectors and ouput them to
> data_vector.
> This is the contents of text_1.txt:
> 0000011111
> 1111100000
> 0000000000
> 1111111111

> This pretty much spits out garbage.  Is there a special
> format files have to be in to read them into vhdl?  I'm
> guessing my problem may be that test_1.txt is an ascii
> file.  If this is a formating problem, how can I generate
> the correct file format?

> FYI - My goal is to use this with vsim/modeltech 5.3 so I
> can test a series of test_vectors without typing the bit
> vectors in by hand.  Does vsim have any features that will
> allow me to do this without writing this extra code.

> Thanks in advance for any help you can provide.
> -Swope

> * Sent from AltaVista http://www.altavista.com Where you can also find related Web Pages, Images, Audios, Videos, News, and Shopping.  Smart is Beautiful



Sat, 01 Feb 2003 03:00:00 GMT  
 reading files in VHDL / vsim
Hi,
    The way you do a "read" is not legal. First you should read a line using
"readline" and then use "read" to read the data. This has been asked so many
times in this NG. (Ediwn would you consider adding up a small example in the
FAQ which could explain the process in a more detailed fashion - TIA)

Also you need the ieee.std_logic_textio package to read std_logic data
types.

Quote:
> Library IEEE;
> use IEEE.std_logic_1164.all;
> use IEEE.std_logic_unsigned.all;
> use IEEE.std_logic_arith.all;

 use IEEE.std_logic_textio.all;

Quote:

> entity test_module is
>   port( data_vector : out std_logic_vector(0 to 9);
>         clk : in std_logic);
> end;

> architecture testing of test_module is
> begin
>   process(clk)
>     type ten_bit_vector is file of std_logic_vector(0 to 9);
>     variable data_read : std_logic_vector(0 to 9);

        variable data_line : line;

Quote:
>     file data_file: ten_bit_vector is in
>         "/u/rsf/code/vhdl/vectors/test_1.txt";
>     begin

  readline (data_file, data_line);
  read(data_line, data_read);

Quote:
>         data_vector <= data_read;
>   end process;
> end testing

The above should do. Of-course you need to add some "EOF" checking etc. (Try
a search on deja.com)

Good Luck,
Srini



Mon, 03 Feb 2003 03:00:00 GMT  
 reading files in VHDL / vsim
Hi,

Quote:

> Hi,
>     The way you do a "read" is not legal. First you should read a line using
> "readline" and then use "read" to read the data. This has been asked so many
> times in this NG. (Ediwn would you consider adding up a small example in the
> FAQ which could explain the process in a more detailed fashion - TIA)

Ok, I'll do it. Thanks for the hint!

--
Edwin



Tue, 04 Feb 2003 03:00:00 GMT  
 
 [ 4 post ] 

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