leonardo/altera/LPM_RAM_DP 
Author Message
 leonardo/altera/LPM_RAM_DP

Hi, all.

I have the following problem: My current design (ACEX (aka cheap 10ke),
synthesis with leonardo) needs some dual ported RAMs. I explicitly instantiate
them, like

Quote:
> m : LPM_RAM_DP
>     GENERIC MAP (lpm_widthad => depthbits,
> [...]
>     PORT MAP (
>         rdclock => clk,
> [...]

Now, unfortunately leonardo does not recognize the modules:

Quote:
> Total accumulated area :
> [...]
>  Black Box lpm_ram_dp_2_10_1024_REGISTERED_REGISTERED_REGISTERED_REGISTERED_

UNUSED_LPM_RAM_DP_UNUSED :     2
Quote:
>  Black Box lpm_ram_dp_8_5_32_REGISTERED_REGISTERED_REGISTERED_REGISTERED_UNU

SED_LPM_RAM_DP_UNUSED :     4

And then the timing analysis is far off reality, as I don't believe
that reading from a registered output could need 5ns.

Quote:
> Critical path #1, (path slack = -4.3):
> [...]
> default arrival at blackbox outputs                                  5.00

As can seen from the slack, I would meet the timing if leonardo would
know the realistic arrival time from the RAM.

Anyone got a similar problem? Would automatic RAM inferring (which I
do not trust) help? Can I tell leonardo anthing about the timing of
the black boxes?

BTW, I know that the timing report from the synthesis tool is not too
usefull at all, but finding the critical paths is easier with leonardo
than with MaxPlus2.

chm.

--
Christian Mautner                           Frequentis Vienna, Austria



Mon, 27 Jan 2003 03:00:00 GMT  
 
 [ 1 post ] 

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