Don't care for integer? 
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 Don't care for integer?

I wan't to know if there is a possibility to define a don't care
for a integer without converting it to a std_logic_vector already
in the vhdl source code?

e.g.
------>8-------------------------------------->8------------
    cnt_init <= 9;                   -- or cnt_init <= '-----'
    case current_state is
      when Z1  =>
      when Z2  => cnt_init <= 9;     -- or cnt_init <= '01001'
                  next_state <= Z2a;
      when Z2a => load <= '0';
      when Z3  => cnt_init <= 29;    -- or cnt_init <= '11101'
                  next_state <= Z3a;
      when Z3a => load <= '0';
    end case;
------8<--------------------------------------8<------------

--
Joerg Schoeppe - Labor Mikroelektronik - FH-Muenchen


Key fingerprint =  C1 58 7A 1E BD 88 75 6B  21 8E 80 78 CB 09 67 7C



Sun, 31 Jan 1999 03:00:00 GMT  
 
 [ 1 post ] 

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