Strange but useful construct: type'(others => '0') 
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 Strange but useful construct: type'(others => '0')

Where the heck does this construct come from:

signal_of_zeros <= std_logic_vector'(others => '0');

This statement will fill signal_of_zeros (a vector) with all zeros.  The '()
doesn't look like a function attribute, doesn't look like a type
attribute, and I've never seen this construct used in any other context.

What is it?



Sat, 08 Mar 1997 05:43:52 GMT  
 Strange but useful construct: type'(others => '0')

Quote:

>Where the heck does this construct come from:

>signal_of_zeros <= std_logic_vector'(others => '0');

>This statement will fill signal_of_zeros (a vector) with all zeros.  The '()
>doesn't look like a function attribute, doesn't look like a type
>attribute, and I've never seen this construct used in any other context.

>What is it?

isn't it an association list?

--




Sat, 08 Mar 1997 07:05:38 GMT  
 Strange but useful construct: type'(others => '0')


Quote:



>>Where the heck does this construct come from:

>>signal_of_zeros <= std_logic_vector'(others => '0');

>>This statement will fill signal_of_zeros (a vector) with all zeros.
The '()
>>doesn't look like a function attribute, doesn't look like a type
>>attribute, and I've never seen this construct used in any other context.

>>What is it?

>isn't it an association list?

It is an aggregate. This one stumped me for a while too.

The name before the tick is a type name. The entire right hand side is an
example of a qualified expression. To quote the LRM'87: "A qualified
expression is used to explicitly state the type, and possibly the
subtype, of an operand that is an expression or an aggregate". Qualified
expressions are used when the type of the aggregate isn't known from the
context.

For this particular case, the type of signal_of_zeros should be known by
the compiler and hence all that is required is:

     signal_of_zeros <= (others => '0');

This is a great way to initialize a signal or variable to zeroes or ones
or anything else. The width of signal is determined automagicly (by most
compilers) and hence if you change the width you don't have to go back
and edit all the code. This *idiom* is used quite frequently by VHDL
writers.

Another example of an aggregate is this:

    signal_that_is_one <= ( 0=>'1', others => '0');

This gives a signal like "0...0001".

Aggregates are "values" of a particular composite type that specify all
of the elements of that type. (Sorry, the LRM definitions are a little
better). What is a composite type? Arrays and records are composite
types. Each is "composed" of elements. Arrays are homogeneous aggregates
(each element is the same as any other). Records are heterogenous types
(each element may be different then any other). (A bag of OREO cookies is
my favorite example of an array aggregate). Each of the elements in the
aggregate can be specified by positional or named association. Positional
association requires you to name the element *and* provide an expression
to assign to that element. Positional association is just like you use
when you make a function call in C. Each argument has to line up with its
corresponding argument in the function declaration. The OTHERS keyword is
handy because it allows you to specify a few of the elements using named
association then permits the remaining ones to be swept under the carpet
easily. (OTHERS => '0') is just a convenient way of saying make
everything zero.

If you happen to define subtypes for bits in a field within a word then
aggregates like this might be handy:

   SUBTYPE alu_op_field IS integer RANGE 3 DOWNTO 0;
   SUBTYPE opcode_field IS integer RANGE 5 DOWNTO 4;
   SUBTYPE source_field IS integer RANGE 7 DOWNTO 6;
   SUBTYPE instruction_type IS bit_vector(7 DOWNTO 0);

   SIGNAL instruction : instruction_type;
...
   -- Assign constant (perhaps default) values
   instruction <= (alu_op_field => '0', opcode_field => '1', source_field
=> '0');
...
   -- Assign specific values
   instruction(alu_op_field) <= "0010";
   instruction(opcode_field) <= "00";
   instruction(source_field) <= "10";

This is a way under-utilized feature of the language syntax and
semantics. When used properly it will increase the self documenting
nature of your description significantly.

To summarize a little BNF ...

   aggregate ::= (element_association { , element_association } )
   element_association ::= [choices => ] expression
   choices ::= choice { | choice }
   choice ::=
       simple_expression
       | discrete_range
       | element_simple_name
       | OTHERS

Have Fun!

...tIM



Sat, 08 Mar 1997 09:47:20 GMT  
 Strange but useful construct: type'(others => '0')
|> Where the heck does this construct come from:
|>
|> signal_of_zeros <= std_logic_vector'(others => '0');
|>
|> This statement will fill signal_of_zeros (a vector) with all zeros.  The '()
|> doesn't look like a function attribute, doesn't look like a type
|> attribute, and I've never seen this construct used in any other context.
|>
|> What is it?
|>
It is a "qualified expression" applied to an "array aggregate".
See LRM 87 or 93, section 7.3.4 and 7.3.2.2.

--

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|__|  /  Center for Computer Science       | Fax:   (+49) 2241 14 2342
|  | /   Schloss Birlinghoven              | Had a nightmare yesterday:
|  |/    53754 St. Augustin, Germany       | My system started up with
                                           | ... Booting vmunix.el ...



Sat, 08 Mar 1997 20:38:46 GMT  
 Strange but useful construct: type'(others => '0')

Quote:


>>Where the heck does this construct come from:

>>signal_of_zeros <= std_logic_vector'(others => '0');

>>This statement will fill signal_of_zeros (a vector) with all zeros.  The '()
>>doesn't look like a function attribute, doesn't look like a type
>>attribute, and I've never seen this construct used in any other context.

>>What is it?

>isn't it an association list?

A qualified expression assigned to a signal.  The more interesting question
is why is the expression qualified?

As expressed in 7.3.4, Qualified Expressions

(the Note)

A qualified expression can be used to state a type explicity when the type
of an aggregate is not known from context.

---

From 7.3.2.2, Array Aggregates

An others choice in an array aggregate (std_logic_vector is an array) can
only appear (number 4.)

  As a value expression in an assignment statement, where the target is
  a declared object, and the subtype of the target is a constrained
  array subtype.

---

Meaning that the array needs to be constrained (Chap 3, Types).

In which case either of the following assignments would work:

library ieee;
use ieee.std_logic_1164.all;

entity foo is
    port (
    signal signal_of_zeros:     out    std_logic_vector (11 downto 0)
    );
end ;

architecture behave of foo is
    begin
    signal_of_zeros <= std_logic_vector'(others => '0');
-- or --
    signal_of_zeros <= (others => '0');
end behave;

---

The question then becomes can the context be ambiguous?  I believe there
is already a requirement to determine if the value ('0') is of the index
type (enumeration literal) of the element type (stand_logic_vector),
(7.3.2.2, Array Aggregates), to determine its numerical (index) value for
assignment.

In other words I don't believe the type mark is required in the assignment
statement.



Sun, 09 Mar 1997 00:07:40 GMT  
 Strange but useful construct: type'(others => '0')

Quote:

>Where the heck does this construct come from:

>signal_of_zeros <= std_logic_vector'(others => '0');

>This statement will fill signal_of_zeros (a vector) with all zeros.  The '()
>doesn't look like a function attribute, doesn't look like a type
>attribute, and I've never seen this construct used in any other context.

>What is it?

The std_logic_vector'() is a type qualifier.  It means that the
expresssion in brackets is of type std_logic_vector.

Wing-Chi



Sun, 09 Mar 1997 02:48:50 GMT  
 Strange but useful construct: type'(others => '0')


Quote:

>|> Where the heck does this construct come from:
>|>
>|> signal_of_zeros <= std_logic_vector'(others => '0');
>|>
>|> This statement will fill signal_of_zeros (a vector) with all zeros.  The '()
>|> doesn't look like a function attribute, doesn't look like a type
>|> attribute, and I've never seen this construct used in any other context.
>|>
>|> What is it?
>|>

>What you are looking at there is a qualified expression consisting of an array aggregate.  This is a way of
>specifying an array value by specifying the type of the value and the value of each array element.  In the
>example, all elements have the value '0'.

>PA

>-------------------------------------------------------------------------

>Dept. Computer Science               /      \      
>University of Adelaide       \_.--*_/       Ph:  +61 8 303 4477
>SA  5005, Australia                v        Fax: +61 8 303 4366

>            http://www.cs.adelaide.edu.au/~petera/

Here is another reply:

=====


Date: Wed, 21 Sep 94 22:00:53 PDT


Subject: Re: Strange but useful construct: type'(others => '0')
Newsgroups: comp.lang.vhdl


Organization: Standard Microsystems Corp - West Coast

I can't post to comp.lang.vhdl, but I can read it...

The proper syntax is:

signal a : std_logic_vector (5 downto 0) := (others => '0');

This means:
a is a std_logic_vector (it has bits 5 down to 0) and each bit
is initialized to '0'.

The 'others' construct is so that you have an easy way to initialize
large things, without having to repeat the '5 downto 0' part.

As I recall, you can get even more tricky, by assigning some of the
bits to specific values, and set the rest to a default, by using 'others'.

We use this a lot - normally to initialize signals to 'U'.

You can post this if you want...
Erik
=====

and here is one example I used.
=====

  SIGNAL   memBank : memArray := (
     0 => B"00000000",
     1 => B"00000000",
    16 => B"10000000",
    17 => B"11000000",
    32 => B"10000000",
    33 => B"01000000",
    34 => B"11000000",
    OTHERS => B"00000000");

==

Lun
--




Tue, 11 Mar 1997 00:41:23 GMT  
 Strange but useful construct: type'(others => '0')
hi all QuickVHDL users:

i am trying to run some VHDL models using QuickVHDL on Falcon V8.4_1.
does qvcom and qvsim require separate licensing because it looks like
QuickVHDL is a part of DA and i guess DA's licensing should hold good for
that also. as of now if i try to run it i get the following message at startup:

//  QuickVHDL qvsim v8.4_1.4.2e Jun 15 1994 SunOS 4.1.3
//
//  Copyright (c) Mentor Graphics Corporation, 1982-1994, All Rights Reserved.
//                       UNPUBLISHED, LICENSED SOFTWARE.
//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
//          PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS.
//
//  Copyright (c) Model Technology Incorporated 1990-1994, All Rights Reserved.
//

//  License request for qvsim feature failed
//  ERROR: License checkout failed

help appreciated !
thanx

- chid



Tue, 11 Mar 1997 06:44:00 GMT  
 Strange but useful construct: type'(others => '0')
hi all QuickVHDL users:
i am a new QuickVHDL user and was trying to run a simple VHDL model using QuickVHDL
on Falcon V8.4_1.
does qvsim and qvcom require separate licenses becos what i felt was that quickVHDL
being a part of DA should be using DA's license, but i get the following message
at startup:

//  QuickVHDL qvsim v8.4_1.4.2e Jun 15 1994 SunOS 4.1.3
//
//  Copyright (c) Mentor Graphics Corporation, 1982-1994, All Rights Reserved.
//                       UNPUBLISHED, LICENSED SOFTWARE.
//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
//          PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS.
//
//  Copyright (c) Model Technology Incorporated 1990-1994, All Rights Reserved.
//

//  License request for qvsim feature failed
//  ERROR: License checkout failed

also a brief outline on the operating procedures would be appreciated
thanx

- chid



Tue, 11 Mar 1997 06:52:35 GMT  
 Strange but useful construct: type'(others => '0')

Thanks, Tim and David, for the well researched and complete answers.
Mystery solved.  The four VHDL books I check didn't mention OTHERS was
a special keyword for use in aggregate assignments.  It sounds like I need
to get myself a copy of the LRM.  I suspect the IEEE is the only source
for this in which case I'm sure I'm in for a big task (any tips on
where to easily purchase the LRM?)


Quote:
>A qualified expression assigned to a signal.  The more interesting question
>is why is the expression qualified?

Only because a lot of the examples I saw had it this way.

Trivia tidbit for y'all:  You can also have an aggregate on the _target_
side of the assignment.   So, the following is legal:

SIGNAL a,b,c : std_logic;
BEGIN
(a,b,c) <= '0';

Pretty useful, I'd say!



Sat, 15 Mar 1997 07:59:17 GMT  
 Strange but useful construct: type'(others => '0')

Quote:

>Thanks, Tim and David, for the well researched and complete answers.
>Mystery solved.  The four VHDL books I check didn't mention OTHERS was
>a special keyword for use in aggregate assignments.  It sounds like I need
>to get myself a copy of the LRM.  I suspect the IEEE is the only source
>for this in which case I'm sure I'm in for a big task (any tips on
>where to easily purchase the LRM?)

To order ANSI/IEEE 1076-1993, try calling ANSI at 212-642-4900.
I think they will take Mastercard or Visa.  The last price I've seen
was $67.50 + postage & handling.  Also FAX at 212-302-1286

Address: 11 West 42nd Street
         New York, NY 10036



Sun, 16 Mar 1997 02:14:46 GMT  
 
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