VHDL FLI/Tcl in Modelsim and wait statement 
Author Message
 VHDL FLI/Tcl in Modelsim and wait statement

Hi, I'm trying to code some test stimulus in Tcl under Modelsim
5.2d. The stimulus driver needs to be triggered on a signal burried
within the DUT's hierarchy. Since VHDL doesn't allow heirarchical
visiblity (ports and/or global packages not an option) I have to use
either Tcl or FLI. I'd prefer Tcl since I don't have time/resources to
invest in FLI, however it seems there is no way to achieve "time
delay" in Tcl.

Specifically this is what I want to do:

 when {/DUT/aBlock/anInst/trigSignal} {
        # wait for some given simulation time  <-- how to achieve this?
        ...
        # force some external signals
        ...
        # wait some more
        ...
        # examine some external/internal signals
 }

From the documenation it's clear than a "run" command can't be used
within a "when" block. So that can't be used to move the simulator
forward in time. Any suggestions?

(Note the "examine some internal signals", I can't trigger off a VHDL
process from Tcl because of that. Got to remain in Tcl.)

BTW any opinions on using Tcl under Modelsim for developing a
resonably complex test environment? anyone gone down that path?
I'm interested in hearing about pitfalls like the one above.

Out of curosity does the VHDL FLI support "wait" statements? if so how
to implement it? I glanced over the examples directory from Modelsim
and didn't find any clues.

--
-Gurpreet.



Thu, 27 Dec 2001 03:00:00 GMT  
 VHDL FLI/Tcl in Modelsim and wait statement


Quote:

> Hi, I'm trying to code some test stimulus in Tcl under Modelsim
> 5.2d. The stimulus driver needs to be triggered on a signal burried
> within the DUT's hierarchy. Since VHDL doesn't allow heirarchical
> visiblity (ports and/or global packages not an option) I have to use
> either Tcl or FLI. I'd prefer Tcl since I don't have time/resources to
> invest in FLI, however it seems there is no way to achieve "time
> delay" in Tcl.

> Specifically this is what I want to do:

>  when {/DUT/aBlock/anInst/trigSignal} {
>         # wait for some given simulation time  <-- how to achieve
this?
>         ...
>         # force some external signals
>         ...
>         # wait some more
>         ...
>         # examine some external/internal signals
>  }

disclaimer: by no means am i a Tcl guru.  nor have i used Tcl with
ModelSim.  this is just my $0.02! 8)

there is a Tcl command "after x" which causes the script to sleep for x
milliseconds.  i suppose the question i should ask is: How is "after x"
interpreted by ModelSim?  Does it cause the script to halt without
incrementing simulation time and then pick up where it left off? (not
what you want)  Or does it interpret "after x" as a VHDL wait condition
and increments time? (what you want).  i suppose you could give it a
shot and hope for the best! 8)  be sure to post back your results.

Ciao,

RoLm

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Thu, 27 Dec 2001 03:00:00 GMT  
 VHDL FLI/Tcl in Modelsim and wait statement
On 11 Jul 1999 15:46:01 GMT, Gurpreet Bhullar

on examining internal signals in VHDL with ModelSim...

Gurpreet,

Have you considered doing the following:

1 - Define a new "trigger" signal within your testbench
2 - Implement a "when" tcl that drives the value of your examining
signal when it changes

For example: Place in a separate file that is sourced after loading
the design:

when { /test_bench/uut/map_one/intermediate } {
 force /test_bench/trigger
$examine(/test_bench/uut/map_one/intermediate)

Quote:
}

(apologies for potential line-wrap)

In this way you can drag a signal through the hierarchy with this
sleight-of-hand and do the rest of your stuff in pure VHDL.

Hope this helps.

Cheers
Stuart

An employee of Saros Technology:
Model Technology, Exemplar Logic, TransEDA, Renoir.
www.saros.co.uk



Fri, 28 Dec 2001 03:00:00 GMT  
 
 [ 3 post ] 

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