final assignment of a internal declared signal and output port 
Author Message
 final assignment of a internal declared signal and output port

I'm learning VHDL;
in some architecture, sometime I encounter:

architecture
signal internal_signal;
begin
    process
        begin_process
       <some operations>
   end_process
output_port <= internal_signal;
end

but I could write

architecture
begin
    process
        begin_process
       <some operations on internal_signal>
   end_process
end

what is the difference in syntesis?
Thanks



Sun, 26 Sep 2004 03:58:29 GMT  
 final assignment of a internal declared signal and output port
Franko,

The difference depends on whether your "internal_signal" is used elsewhere
in the same module.  If it is, then your choices are either:

1. use the first example and declare output_port as type out, or
2. use the second example and declare output_port as type buffer.

Generally, it is better practice to avoid using the port type buffer to
avoid problems sharing code with others.  In all cases do not use port type
buffer for top level I/O.  This is because any model that you get back after
synthesis will not use type buffer, and you will have a mismatch in the port
declarations between your RTL and the post synthesis model.

Regards,

Quote:
> I'm learning VHDL;
> in some architecture, sometime I encounter:

> architecture
> signal internal_signal;
> begin
>     process
>         begin_process
>        <some operations>
>    end_process
> output_port <= internal_signal;
> end

> but I could write

> architecture
> begin
>     process
>         begin_process
>        <some operations on internal_signal>
>    end_process
> end

> what is the difference in syntesis?
> Thanks



Sun, 26 Sep 2004 07:03:38 GMT  
 final assignment of a internal declared signal and output port

Quote:

> in some architecture, sometime I encounter:
> architecture
> signal internal_signal;
> begin
>     process
>         begin_process
>        <some operations>
>    end_process
> output_port <= internal_signal;
> end
> but I could write
> architecture
> begin
>     process
>         begin_process
>        <some operations on internal_signal>
>    end_process
> end
> what is the difference in syntesis?

In the first case an entity output port is wired
to signal presumably driven by the process.

In the second case, no connection to the
port is shown, unless you meant that to
be part of

<some operations on internal_signal>

If a signal is not involved in driving
some entity port it is ignored for synthesis.

A port assignment outside a process makes a wire.

A port assignment inside a process can make a wire, latch or register.

 -- Mike Treseler



Sun, 26 Sep 2004 07:38:59 GMT  
 
 [ 3 post ] 

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