procedure + wait statement 
Author Message
 procedure + wait statement

In the process example I call the procedure send. The simulator
complains about illegal VHDL, but according to the Language Reference Manual
(VHDL93) a wait statement is possible in a procedure, as long as this
procedure wont be called in a process with a sensitivity-list, which
process 'example' doesnt. What seems to be the problem here?

Thanks already,

Ramon

Test.vhd:

entity proces1 is
end entity proces1;

architecture behav of proces1 is

procedure send is
begin
 wait for 1 sec;
end procedure;

BEGIN

example : process
begin
wait for 5 sec;
send;
end process example;

end architecture behav;

Simulator output:

Symphony EDA (R) VHDL Compiler/Simulator Module VhdlE, Version 1.4,
Build#10.
Copyright(C) Symphony EDA 1997-1999. All rights reserved.
Reading C:\Program Files\Symphony EDA\VHDL Simili\bin\symphony.ini ...
Library 'ieee'          ==> $SYMPHONY/Lib/Ieee/Ieee.sym
Library 'work'          ==> work.sym
Reading  work.sym\proces2\proces1.var
Reading  work.sym\proces2\proces1(behav).var
        # of Signals       = 0
        # of Components    = 0
        # of Processes     = 1
        # of Drivers       = 0
Design Load/Elaboration Elapsed Time: 00h:00m:00s:073ms
Error: CSSIM0012: test.vhd: (line 10): Illegal use of wait stmt.
Non-existent parent process or parent process does not allow wait statements
Time: 5 sec+0
    At test.vhd: (line 10)
        Instance = :proces1(behav):send:
    At test.vhd: (line 18)
        Instance = :proces1(behav)
Exception occurred. Cannot continue simulation



Mon, 06 May 2002 03:00:00 GMT  
 procedure + wait statement
That is perfectly legal VHDL and yes
we do support that. Let me
take a look at what went wrong.

Regards,
Haneef
Symphony EDA


Quote:
> In the process 'example' I call the procedure 'send'. The simulator
> complains about illegal VHDL, but according to the Language Reference
Manual
> (VHDL93) a wait statement is possible in a procedure, as long as this
> procedure won't be called in a process with a sensitivity-list, which
> process 'example' doesn't. What seems to be the problem here?



Mon, 06 May 2002 03:00:00 GMT  
 procedure + wait statement


Quote:
> In the process "example" I call the procedure "send". The simulator
> complains about illegal VHDL, but according to the Language
> Reference Manual (VHDL93) a wait statement is possible in a
> procedure, as long as this procedure won't be called in a process
> with a sensitivity-list, which process 'example' doesn't. What seems
> to be the problem here?

Um, a buggy tool?  The model looks perfectly legal to me.

Paul

--

Cadence Design Systems | www.orcad.com   | spread fear, uncertainty and
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Durham, NC  27722-1767 | 919-479-1671[f] |  --Don Jones, MS's Y2K Product Mgr



Mon, 06 May 2002 03:00:00 GMT  
 procedure + wait statement

Quote:

> In the process ?example? I call the procedure ?send?. The simulator
> complains about illegal VHDL, but according to the Language Reference Manual
> (VHDL93) a wait statement is possible in a procedure, as long as this
> procedure won?t be called in a process with a sensitivity-list, which
> process 'example' doesn?t. What seems to be the problem here?

> Thanks already,

> Ramon

> Test.vhd:

> entity proces1 is
> end entity proces1;

> architecture behav of proces1 is

> procedure send is
> begin
>  wait for 1 sec;
> end procedure;

> BEGIN

> example : process
> begin
> wait for 5 sec;
> send;
> end process example;

> end architecture behav;

> Simulator output:

> Symphony EDA (R) VHDL Compiler/Simulator Module VhdlE, Version 1.4,
> Build#10.
> Copyright(C) Symphony EDA 1997-1999. All rights reserved.
> Reading C:\Program Files\Symphony EDA\VHDL Simili\bin\symphony.ini ...
> Library 'ieee'          ==> $SYMPHONY/Lib/Ieee/Ieee.sym
> Library 'work'          ==> work.sym
> Reading  work.sym\proces2\proces1.var
> Reading  work.sym\proces2\proces1(behav).var
>         # of Signals       = 0
>         # of Components    = 0
>         # of Processes     = 1
>         # of Drivers       = 0
> Design Load/Elaboration Elapsed Time: 00h:00m:00s:073ms
> Error: CSSIM0012: test.vhd: (line 10): Illegal use of wait stmt.
> Non-existent parent process or parent process does not allow wait statements
> Time: 5 sec+0
>     At test.vhd: (line 10)
>         Instance = :proces1(behav):send:
>     At test.vhd: (line 18)
>         Instance = :proces1(behav)
> Exception occurred. Cannot continue simulation

Leapfrog detects no errors in your code.

Regards,
--
Renaud Pacalet, ENST / COMELEC, 46 rue Barrault 75634 Paris Cedex 13

LIVIC,  Batiment  140,  13  route  de  la  Minire  78000 Versailles



Tue, 07 May 2002 03:00:00 GMT  
 
 [ 4 post ] 

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