Generics at testbench level 
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 Generics at testbench level

How do I handle a case were I want to use a generic at the testbench
level so I can test various port widths?  Given the following design,
how do I set the value of DWIDTH in a_arch_tb?

------------ design to be tested -----
library ieee;
use ieee.std_logic_1164.all;
entity a_ent is
   generic ( DWIDTH : integer );
   port (
      clk         : in std_logic;
      d           : in std_logic_vector(DWIDTH-1 downto 0);
      q           : out std_logic_vector(DWIDTH-1 downto 0) );
end a_ent;

architecture a_arch of a_ent is
begin  --a_arch
   a_proc : process (Clk)
   begin --  a_proc
      if (Clk'event and Clk = '1') then
         q <= d;
      end if;
   end process a_proc;
end a_arch;

------------- testbench ---------------
library ieee;
use ieee.std_logic_1164.all;
entity a_ent_tb is
   generic ( DWIDTH : integer );
end a_ent_tb;

architecture a_arch_tb of a_ent_tb is
   component a_ent port (
      clk         : in std_logic := '0';
      d           : in std_logic_vector(DWIDTH-1 downto 0);
      q           : out std_logic_vector(DWIDTH-1 downto 0) );
   end component;
   signal clk           : std_logic;
   signal d             : std_logic_vector(DWIDTH-1 downto 0);
   signal q             : std_logic_vector(DWIDTH-1 downto 0);

begin  --a_arch_tb
   UUT : a_ent port map (
      clk => clk, d => d, q => q );

   main : process
   begin --  main
      d <= (others => '0');
      wait for 40 ns;
      d <= (others => '1');
      wait;
   end process main;

   clock : process
   begin --  clock
      clk <= '0';
      wait for 20 ns;
      clk <= '1';
      wait for 20 ns;
   end process clock;
end a_arch_tb;

------------- configs ---------------
configuration tb_cfg1 of a_ent_tb is
   for a_arch_tb
      for UUT : a_ent
         use entity work.a_ent(a_arch)
         generic map (
            DWIDTH => 8 );
      end for;
   end for;
end tb_cfg1;

configuration tb_cfg2 of a_ent_tb is
   for a_arch_tb
      for UUT : a_ent
         use entity work.a_ent(a_arch)
         generic map (
            DWIDTH => 32 );
      end for;
   end for;
end tb_cfg2;

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Sat, 26 Jan 2002 03:00:00 GMT  
 Generics at testbench level
Top-level generics, like the one declared in a_ent,  can be set on the
command line of most simulators, or in the GUI when you load a design.
If you are using MTI, there is a "VHDL" tab on the Load Design dialog box
where you can set the generic value.

-Kurt
Kurt Schwartz
Willamette HDL, Inc.
VHDL and Verilog training and consulting

www.whdl.com

Quote:

> How do I handle a case were I want to use a generic at the testbench
> level so I can test various port widths?  Given the following design,
> how do I set the value of DWIDTH in a_arch_tb?

> ------------ design to be tested -----
> library ieee;
> use ieee.std_logic_1164.all;
> entity a_ent is
>    generic ( DWIDTH : integer );
>    port (
>       clk         : in std_logic;
>       d           : in std_logic_vector(DWIDTH-1 downto 0);
>       q           : out std_logic_vector(DWIDTH-1 downto 0) );
> end a_ent;

> architecture a_arch of a_ent is
> begin  --a_arch
>    a_proc : process (Clk)
>    begin --  a_proc
>       if (Clk'event and Clk = '1') then
>          q <= d;
>       end if;
>    end process a_proc;
> end a_arch;

> ------------- testbench ---------------
> library ieee;
> use ieee.std_logic_1164.all;
> entity a_ent_tb is
>    generic ( DWIDTH : integer );
> end a_ent_tb;

> architecture a_arch_tb of a_ent_tb is
>    component a_ent port (
>       clk         : in std_logic := '0';
>       d           : in std_logic_vector(DWIDTH-1 downto 0);
>       q           : out std_logic_vector(DWIDTH-1 downto 0) );
>    end component;
>    signal clk           : std_logic;
>    signal d             : std_logic_vector(DWIDTH-1 downto 0);
>    signal q             : std_logic_vector(DWIDTH-1 downto 0);

> begin  --a_arch_tb
>    UUT : a_ent port map (
>       clk => clk, d => d, q => q );

>    main : process
>    begin --  main
>       d <= (others => '0');
>       wait for 40 ns;
>       d <= (others => '1');
>       wait;
>    end process main;

>    clock : process
>    begin --  clock
>       clk <= '0';
>       wait for 20 ns;
>       clk <= '1';
>       wait for 20 ns;
>    end process clock;
> end a_arch_tb;

> ------------- configs ---------------
> configuration tb_cfg1 of a_ent_tb is
>    for a_arch_tb
>       for UUT : a_ent
>          use entity work.a_ent(a_arch)
>          generic map (
>             DWIDTH => 8 );
>       end for;
>    end for;
> end tb_cfg1;

> configuration tb_cfg2 of a_ent_tb is
>    for a_arch_tb
>       for UUT : a_ent
>          use entity work.a_ent(a_arch)
>          generic map (
>             DWIDTH => 32 );
>       end for;
>    end for;
> end tb_cfg2;

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> Share what you know. Learn what you don't.



Sat, 26 Jan 2002 03:00:00 GMT  
 Generics at testbench level

Seamus,
      When you instanciate the a_ent entity within your test bench, you can
have a fixed value DWIDTH  by means of the generic map e.g

DWIDTH => 16

If you are using MTI then if you want to simulate this for a number of
different values you can do this as follows (example using VSIM)

A batch file could be used as follows (assuming tba_ent is the test bench
entity name) which contains the lines

vsim -do run.do -GDWIDTH=8 -lib work tba_ent
vsim -do run.do -GDWIDTH=16-lib work tba_ent
vsim -do run.do -GDWIDTH=32 -lib work tba_ent

with run.do a macro as follows

run 10000 ns
quit -force

-g or -G can be used

                  regards
                            David Murray



Sun, 27 Jan 2002 03:00:00 GMT  
 
 [ 3 post ] 

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