I'm trying to integrate VHDL component within Handel-C code( project)  ,
anybody can give me a simple example in order to show me how to connecting
Handel-C EDIF to VHDL code,  only use handel-c DK1( also common line) and
Xilinx Foundation command line(such as  ngdbuild, map, par, bitgen) .

According to Handel-C User Manual, it use the word "connect", but the format
of  the output EDIF file of Handel-C is far more different from the format
of VHDL code......

I mean I know how to code VHDL and Handel-C, but I don't know the detailed
course of connecting them together.

Thanks in advance ....

Regards,

Stella