connecting EDIF to VHDL 
Author Message
 connecting EDIF to VHDL

Hi, Guys:

I'm trying to integrate VHDL component within Handel-C code( project)  ,
anybody can give me a simple example in order to show me how to connecting
Handel-C EDIF to VHDL code,  only use handel-c DK1( also common line) and
Xilinx Foundation command line(such as  ngdbuild, map, par, bitgen) .

According to Handel-C User Manual, it use the word "connect", but the format
of  the output EDIF file of Handel-C is far more different from the format
of VHDL code......

I mean I know how to code VHDL and Handel-C, but I don't know the detailed
course of connecting them together.

Thanks in advance ....



Sun, 11 Jul 2004 20:28:24 GMT  
 [ 1 post ] 

 Relevant Pages 

1. LeonardoSpectrum for Altera, VHDL -> EDIF conversion

2. Edif and VHDL

3. Converting EDIF files or Viewdraw Schematics to VHDL

4. vhdl to blif (or edif ?)

5. EDIF to VHDL, second try

6. EDIF to VHDL survey results

7. EDIF to VHDL translator

8. edif to VHDL Translator.

9. VHDL-EDIF interoperability

10. EDIF 2 VHDL ?

11. EDIF to VHDL

12. edif to vhdl translator


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