**ANNOUNCEMENT: VHDL to Verilog Translator** 
Author Message
 **ANNOUNCEMENT: VHDL to Verilog Translator**

ANNOUNCING THE RELEASE OF ASC's VHDL to Verilog TRANSLATOR, VHDL2verilog(TM)
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VHDL2verilog translates hierarchical VHDL to functionally equivalent Verilog
HDL. All structural VHDL constructs, as well as a large subset of RTL VHDL
constructs are supported by VHDL2verilog. Both IEEE Standard 1076-1987 and
1076-1993 compliant VHDL are processed by the tool. Output Verilog follows
the proposed IEEE-1364 standard, and is easy to understand.  Product
description can be found at http://www.*-*-*.com/ ;                  

VHDL2verilog can also be obtained with an object-oriented Software Procedural
Interface (SPI) to access the output HDL and is currently available for SunOS
4.1.x platform.

An immediate demo is available at http://www.*-*-*.com/

All enquiries to:
----------------

Jon Clancy
Alternative System Concepts, Inc.  PO Box 128 Windham NH 03087
Ph:(603)437-2234 Fax: (603)437-2722

--
*       Sashi Obilisetty                                                        *
*       Alternative System Concepts, Inc.                                       *
*       PO Box 128 Windham NH 03087                                             *
*       tel (603) 437-2234 fax (603) 437-ASC2   URL http://www.*-*-*.com/     *



Sun, 19 Apr 1998 03:00:00 GMT  
 
 [ 1 post ] 

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